ADSST-SHARC-MEL-100_15 Datasheet, PDF (1/28 Pages) Analog Devices – SHARC Mel-100 Audio Processor

SUMMARY
High performance 32-bit audio processor
Super Harvard Architecture Computer (SHARC)
4 independent buses for dual data, instruction, and
nonintrusive, zero-overhead I/O fetch on a single cycle
Code compatible with all other SHARC family DSPs
Single-instruction-multiple-data (SIMD) computational
architecture—two 32-bit IEEE floating-point computa-
tion units, each with a multiplier, ALU, shifter, and
register file
SHARC^® Mel-100
Audio Processor
ADSST-SHARC-Mel-100
Serial ports offer I²S support via 8 programmable and
simultaneous receive or transmit pins, which support up
to 16 transmit or 16 receive channels of audio
Integrated peripherals—integrated I/O processor,
0.5 Mbit on-chip SRAM, SDRAM controller, glueless
multiprocessing features, and I/O ports (serial, link,
external bus, SPI®, and JTAG)
SHARC Mel-100 supports 32-bit fixed-point, 32-bit
floating-point, and 40-bit floating-point formats
CORE PROCESSOR
TIMER
INSTRUCTION
CACHE
32 × 48-BIT
DAG1
8 × 4 × 32
DAG2
8 × 4 × 32
PROGRAM
SEQUENCER
BUS
CONNECT
(PX)
32
PM ADDRESS BUS
32
DM ADDRESS BUS
64
PM DATA BUS
64
DM DATA BUS
DUAL-PORTED SRAM
TWO INDEPENDENT
DUAL-PORTED BLOCKS
PROCESSOR PORT
I/O PORT
ADDR
DATA
DATA
ADDR
ADDR
DATA
DATA
ADDR
IOD
IOA
64
18
MULT
DATA
REGISTER
FILE
(PEX)
16 × 40-BIT
BARREL
SHIFTER
BARREL
SHIFTER
DATA
REGISTER
FILE
(PEY)
16 × 40-BIT
MULT
JTAG
6
TEST & EMULATION
12
GPIO
FLAGS
8
SDRAM
CONTROLLER
EXTERNAL PORT
ADDR BUS
24
MUX
MULTIPROCESSOR
INTERFACE
DATA BUS
32
MUX
HOST PORT
ALU
ALU
IOP
REGISTERS
DMA
5
CONTROLLER
16
(MEMORY MAPPED)
SERIAL PORTS (4)
CONTROL,
STATUS, AND
DATA BUFFERS
20
LINK PORTS (2)
4
SPI PORTS (1)
I/O PROCESSOR
Figure 1. Functional Block Diagram
Rev. 0
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