ADSP-2187LBSTZ-210 Datasheet, PDF (18/48 Pages) Analog Devices – DSP Microcomputer

ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L
Table 9. Common-Mode Pins (Continued)
Pin Name
No. of Pins
I/O
Function
V_DDINT
V_DDEXT
GND
4
I
Internal V_DD (3.3 V) Power (BGA)
7
I
External V_DD (3.3 V) Power (BGA)
20
I
Ground (BGA)
EZ-Port
9
I/O
For Emulation Use
1 _{Interrupt/Flag pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, the DSP will vector to the appropriate interrupt vector address}
when the pin is asserted, either by external devices or set as a programmable flag.
2 _{This mode applies to the ADSP-2187L only.}
3 _{SPORT configuration determined by the DSP System Control Register. Software configurable.}
MEMORY INTERFACE PINS
ADSP-218xL series members can be used in one of two modes:
Full Memory Mode, which allows BDMA operation with full
external overlay memory and I/O capability, or Host Mode,
which allows IDMA operation with limited external addressing
capabilities.
The operating mode is determined by the state of the Mode C
pin during RESET and cannot be changed while the processor is
running. Table 10 and Table 11 list the active signals at specific
pins of the DSP during either of the two operating modes (Full
Memory or Host). A signal in one table shares a pin with a sig-
nal from the other table, with the active signal determined by
the mode that is set. For the shared pins and their alternate sig-
nals (e.g., A4/IAD3), refer to the package pinouts in Table 29 on
Page 44 and Table 30 on Page 45.
Table 10. Full Memory Mode Pins (Mode C = 0)
Pin Name
A13 – 0
D23 – 0
No. of Pins I/O
14
O
24
I/O
Function
Address Output Pins for Program, Data, Byte, and I/O Spaces
Data I/O Pins for Program, Data, Byte, and I/O Spaces (8 MSBs are also used as Byte Memory
Addresses.)
Table 11. Host Mode Pins (Mode C = 1)
Pin Name
No. of Pins I/O
Function
IAD15 – 0
16
A0
1
I/O
IDMA Port Address/Data Bus
O
Address Pin for External I/O, Program, Data, or Byte Access¹
D23 – 8
16
I/O
Data I/O Pins for Program, Data, Byte, and I/O Spaces
IWR
1
I
IDMA Write Enable
IRD
1
I
IDMA Read Enable
IAL
1
I
IDMA Address Latch Pin
IS
1
IACK
1
I
IDMA Select
O
IDMA Port Acknowledge Configurable in Mode D²; Open Drain
1 _{In Host Mode, external peripheral addresses can be decoded using the A0, CMS, PMS, DMS, and IOMS signals.}
2 _{Mode D function available on ADSP-2187L only.}
Rev. C | Page 18 of 48 | January 2008