ADSP-2187LBSTZ-210 Datasheet, PDF (1/48 Pages) Analog Devices – DSP Microcomputer

DSP Microcomputer
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L
PERFORMANCE FEATURES
Up to 19 ns instruction cycle time, 52 MIPS sustained
performance
Single-cycle instruction execution
Single-cycle context switch
3-bus architecture allows dual operand fetches in every
instruction cycle
Multifunction instructions
Power-down mode featuring low CMOS standby power dissi-
pation with 400 CLKIN cycle recovery from power-down
condition
Low power dissipation in idle mode
INTEGRATION FEATURES
ADSP-2100 family code compatible (easy to use algebraic
syntax), with instruction set extensions
Up to 160K bytes of on-chip RAM, configured
Up to 32K words program memory RAM
Up to 32K words data memory RAM
Dual-purpose program memory for both instruction and
data storage
Independent ALU, multiplier/accumulator, and barrel shifter
computational units
2 independent data address generators
Powerful program sequencer provides zero overhead loop-
ing conditional instruction execution
Programmable 16-bit interval timer with prescaler
100-lead LQFP and 144-ball BGA
SYSTEM INTERFACE FEATURES
16-bit internal DMA port for high-speed access to on-chip
memory (mode selectable)
4M-byte memory interface for storage of data tables and pro-
gram overlays (mode selectable)
8-bit DMA to byte memory for transparent program and data
memory transfers (mode selectable)
Programmable memory strobe and separate I/O memory
space permits “glueless” system design
Programmable wait state generation
2 double-buffered serial ports with companding hardware
and automatic data buffering
Automatic booting of on-chip program memory from byte-
wide external memory, for example, EPROM, or through
internal DMA Port
6 external interrupts
13 programmable flag pins provide flexible system signaling
UART emulation through software SPORT reconfiguration
ICE-Port emulator interface supports debugging in final
systems
DATA ADDRESS
GENERATORS
DAG1 DAG2
PROGRAM
SEQUENCER
POWER-DOWN
CONTROL
MEMORY
PROGRAM
MEMORY
UP TO
32K ؋ 24-BIT
DATA
MEMORY
UP TO
32K ؋ 16-BIT
PROGRAMMABLE
I/O
AND
FLAGS
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
ARITHMETIC UNITS
ALU
MAC SHIFTER
ADSP-2100 BASE
ARCHITECTURE
SERIAL PORTS
SPORT0 SPORT1
TIMER
FULL MEMORY MODE
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
BYTE DMA
CONTROLLER
OR
EXTERNAL
DATA
BUS
INTERNAL
DMA
PORT
HOST MODE
ICE-Port is a trademark of Analog Devices, Inc.
Figure 1. Functional Block Diagram
Rev. C
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