ADSP-21160N_15 Datasheet, PDF (16/60 Pages) Analog Devices – SHARC Digital Signal Processor

ADSP-21160M/ADSP-21160N
ELECTRICAL CHARACTERISTICS—ADSP-21160M
Table 6 shows ADSP-21160M electrical characteristics. These
specifications are subject to change without notification.
Table 6. Electrical Characteristics—ADSP-21160M
Parameter
Test Conditions
Min
Max
Unit
V_OH
V_OL
I_IH
I_IL
I_ILPU1
I_ILPU2
I_OZH
I_OZL
I_OZHPD
I_OZLPU1
I_OZLPU2
I_OZHA
I_OZLA
I_DD-INPEAK
I_DD-INHIGH
I_DD-INLOW
I_DD-IDLE
AI_DD
C_IN
High Level Output Voltage¹
Low Level Output Voltage¹
High Level Input Current^{3, 4, 5}
Low Level Input Current³
Low Level Input Current Pull-Up1⁴
Low Level Input Current Pull-Up2⁵
Three-State Leakage Current^{6, 7, 8, 9}
Three-State Leakage Current⁶
Three-State Leakage Current Pull-Down⁹
Three-State Leakage Current Pull-Up1⁷
Three-State Leakage Current Pull-Up2⁸
Three-State Leakage Current¹⁰
Three-State Leakage Current¹⁰
Supply Current (Internal)¹¹
Supply Current (Internal)¹²
Supply Current (Internal)¹³
Supply Current (Idle)¹⁴
Supply Current (Analog)¹⁵
Input Capacitance^{16, 17}
@ V_DDEXT = Min, I_OH= –2.0 mA²
@ V_DDEXT = Min, I_OL = 4.0 mA²
@ V_DDEXT = Max, V_IN = V_DD Max
@ V_DDEXT = Max, V_IN = 0 V
@ V_DDEXT = Max, V_IN = 0 V
@ V_DDEXT = Max, V_IN = 0 V
@ V_DDEXT = Max, V_IN = V_DD Max
@ V_DDEXT = Max, V_IN = 0 V
@ V_DDEXT = Max, V_IN = V_DD Max
@ V_DDEXT = Max, V_IN = 0 V
@ V_DDEXT = Max, V_IN = 0 V
@ V_DDEXT = Max, V_IN = V_DD Max
@ V_DDEXT = Max, V_IN = 0 V
t_CCLK = 12.5 ns, V_DDINT = Max
t_CCLK = 12.5 ns, V_DDINT = Max
t_CCLK = 12.5 ns, V_DDINT = Max
t_CCLK = 12.5 ns, V_DDINT = Max
@AV_DD= Max
f_IN= 1 MHz, T_CASE = 25°C, V_IN= 2.5 V
2.4
V
0.4
V
10
μA
10
μA
250
μA
500
μA
10
μA
10
μA
250
μA
250
μA
500
μA
25
μA
4
mA
1400
mA
875
mA
625
mA
400
mA
10
mA
4.7
pF
1 _{Applies to output and bidirectional pins: DATA63–0, ADDR31–0, MS3–0, RDx, WRx, PAGE, CLKOUT, ACK, FLAG3–0, TIMEXP, HBG, REDY, DMAG1, DMAG2, BR6–1,}
PA, BRST, CIF, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT7–0, LxCLK, LxACK, BMS, TDO, and EMU.
2 _{See Output Drive Currents—ADSP-21160M on Page 47 for typical drive current capabilities.}
3 _{Applies to input pins: SBTS, IRQ2–0, HBR, CS, ID2–0, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK, and CLK_CFG3-0.}
4 _{Applies to input pins with internal pull-ups: DR0, and DR1.}
5 _{Applies to input pins with internal pull-ups: DMARx, TMS, TDI, and TRST.}
6 _{Applies to three-statable pins: DATA63–0, ADDR31–0, PAGE, CLKOUT, ACK, FLAG3–0, REDY, HBG, BMS, BR6–1, TFSx, RFSx, and TDO.}
7 _{Applies to three-statable pins with internal pull-ups: DTx, TCLKx, RCLKx, and EMU.}
8 _{Applies to three-statable pins with internal pull-ups: MS3–0,RDx, WRx, DMAGx, PA, and CIF.}
9 _{Applies to three-statable pins with internal pull-downs: LxDAT7–0, LxCLK, and LxACK.}
10_{Applies to ACK pulled up internally with 2 k during reset or ID2–0 = 00x.}
11_{The test program used to measure IDD-INPEAK represents worst-case processor operation and is not sustainable under normal application conditions. Actual internal power}
measurements made using typical applications are less than specified. For more information, see Power Dissipation on Page 47.
12_{IDD-INHIGH is a composite average based on a range of high activity code. For more information, see Power Dissipation on Page 47.}
13_{IDD-INLOW is a composite average based on a range of low activity code. For more information, see Power Dissipation on Page 47.}
14_{Idle denotes ADSP-21160M state during execution of IDLE instruction. For more information, see Power Dissipation on Page 47.}
15_{Characterized, but not tested.}
16_{Applies to all signal pins.}
17_{Guaranteed, but not tested.}
Rev. C | Page 16 of 60 | February 2013