ADSP-21160N_15 Datasheet, PDF (1/60 Pages) Analog Devices – SHARC Digital Signal Processor

SUMMARY
High performance 32-bit DSP—applications in audio, medi-
cal, military, graphics, imaging, and communication
Super Harvard architecture—4 independent buses for dual
data fetch, instruction fetch, and nonintrusive, zero-over-
head I/O
Backward compatible—assembly source level compatible
with code for ADSP-2106x DSPs
Single-instruction, multiple-data (SIMD) computational
architecture—two 32-bit IEEE floating-point computation
units, each with a multiplier, ALU, shifter, and register file
Integrated peripherals—integrated I/O processor, 4M bits
on-chip dual-ported SRAM, glueless multiprocessing fea-
tures, and ports (serial, link, external bus, and JTAG)
SHARC
Digital Signal Processor
ADSP-21160M/ADSP-21160N
FEATURES
100 MHz (10 ns) core instruction rate (ADSP-21160N)
Single-cycle instruction execution, including SIMD opera-
tions in both computational units
Dual data address generators (DAGs) with modulo and bit-
reverse addressing
Zero-overhead looping and single-cycle loop setup, provid-
ing efficient program sequencing
IEEE 1149.1 JTAG standard Test Access Port and on-chip
emulation
400-ball 27 mm × 27 mm PBGA package
Available in lead-free (RoHS compliant) package
200 million fixed-point MACs sustained performance
(ADSP-21160N)
CORE PROCESSOR
TIMER
INSTRUCTION
CACHE
32 x 48-BIT
DAG1
DAG2
8 x 4 x 32 8 x 4 x 32
PROGRAM
SEQUENCER
PM ADDRESS BUS
32
DM ADDRESS BUS
32
BUS
CONNECT
(PX)
PM DATA BUS 16/32/40/48/64
DM DATA BUS
32/40/64
DUAL-PORTED SRAM
TWO INDEPENDENT
DUAL-PORTED BLOCKS
PROCESSOR PORT
I/O PORT
ADDR
DATA
DATA ADDR
ADDR
DATA
DATA ADDR
IOD
IOA
64
18
JTAG
6
TEST AND
EMULATION
EXTERNAL
PORT
ADDR BUS
32
MUX
MULTIPROCESSOR
INTERFACE
64
DATA BUS
MUX
HOST PORT
MULT
DATA
REGISTER
FILE
(PEX)
16 x 40-BIT
BARREL
SHIFTER
ALU
BARREL
SHIFTER
DATA
REGISTER
FILE
(PEY)
16 x 40-BIT
MULT
ALU
IOP
REGISTERS
(MEMORY
MAPPED)
DMA
4
CONTROLLER
6
SERIAL PORTS
(2)
6
CONTROL,
STATUS AND
LINK PORTS
60
DATA BUFFERS
(6)
I/O PROCESSOR
Figure 1. Functional Block Diagram
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: [phone]
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com