AD1672_15 Datasheet, PDF (15/20 Pages) Analog Devices – Complete 12-Bit, 3 MSPS Monolithic A/D Converter

AD1672
and/or offset adjustment purposes. Onboard data buffers are
also included. The AD1672/EB requires an external clock
which is applied from a user’s bench or generated from a circuit
built on the prototyping area. A standard 40-pin IDC-connector
provides access for the digital outputs from the AD1672/EB. The
user must also provide a digital +5 V power supply and analog
± 5 V supplies to operate the AD1672/EB.
The AD1672’s analog input range can be configured for
0 V–2.5 V, 0 V–5 V, or ± 2.5 V by installing only one of the four
jumpers, JP5–JP7, as outline in Table VII.
JP5 Installing only jumper JP5, the 0 V–2.5 V range of the
AD1672 is selected.
JP6 Installing only jumper JP6, the 0 V–5 V range of the
AD1672 is selected.
OPERATING PROCEDURE AND FUNCTIONAL
DESCRIPTION
JP7 Installing only jumper JP7, the ± 2.5 V range of the
AD1672 is selected.
Power
Apply power to the AD1672/EB by attaching banana plugs to
Table VII. Analog Input Range Selection
the appropriate banana jacks on the printed circuit board (Fig-
OBSOLETE ure 31). The +VCC analog supply should be +5 V (±5%) and
be capable of supplying 70 mA. The –V_EE analog supply should
be –5 V (± 5%) and be capable of supplying 20 mA. The +V_DD
digital supply should be +5 V (± 5%) and be capable of supply-
ing 12 mA (not including any additional current required by the
digital load).
The power supply pin for the onboard output drivers internal to
the AD1672 (DRV_DD–Pin 14) can be driven directly by the
digital supply, +V_DD, by installing JP10 or may be driven via a
separate supply by removing JP10 and driving the test point,
TP5. The separate supply option allows the user to interface
with +5 V or +3.3 V (± 5%) logic families.
JP1 To provide +V_CC supply to both U3 (DAC08) and U1
(op amp), attach jumper JP1.
JP10 To provide +5 V (+/-5%) supply to DRV_DD pin of
AD1672 via +V_DD or separate supply. To provide power
to DRV_DD pin via +V_DD, install JP10. To provide power
Analog Input Range
(Volts)
0 to 2.5
0 to 5.0
± 2.5
JP5
ON
OFF
OFF
JP6
OFF
ON
OFF
JP7
OFF
OFF
ON
Reference
An external 2.5 V voltage reference, U2, is also included on the
AD1672/EB to provide the option for greater dc precision than
the AD1672’s internal reference. The external reference also
provides the proper biasing currents for the offset adjustment
circuitry consisting of U3. To use the external voltage reference
for the AD1672, install JP9 and remove JP4. To use the AD1672’s
internal voltage reference, install JP4 and remove JP9.
JP4 Installing JP4 and removing JP9 selects the AD1672’s
internal reference.
JP9 Installing JP9 and removing JP4 selects the external
to DRV_DD pin via separate supply, remove JP10 and con-
reference, U2.
nect external supply to test point TP5.
Offset Adjustment/Reconstruction DAC
Analog Inputs
An 8-bit complementary current output DAC08, U3, allows for
The BNC jack, AIN (J1), accepts voltage inputs that comply
either offset adjustment of the analog input or reconstruction of
with the analog input requirements of the AD1672. It is termi- ^{the AD1672 digital output for simple evaluation purposes. The}
nated with a 49.9 Ω resistor (R1) located on the component-
offset adjustment option is implemented by installing both JP3
side of the evaluation board. Remove and/or replace this
and JP8. Note that JP5, JP6 and JP7 should be removed so
resistor with other values in order to match different cable im- ^{that the AD1672 is configured for a 0 V–5 V range.}
pedances. The AD1672 analog input can be directly driven via
AIN (J1) by installing JP2 and removing JP3 or it can be driven
via an amplifier (U1) by installing JP3 and removing JP2. The
amplifier (U1) may be configured in the inverting or noninvert-
ing mode with a gain of one by configuring S4.
The DAC08 can also be configured to reconstruct the digital
output of the AD1672 using its digital output for the DAC08’s
digital input. The output of the user supplied ribbon cable used
to interface with the 40-pin IDC connector (E1) can be con-
nected directly to the connector U8, hence recirculating the
JP2 Installing JP2 and removing JP3, directly dc couples AIN ^{eight most significant digital output bits of the AD1672. In this}
(J1) to the AD1672 analog input.
configuration, JP8 would be removed and the reconstructed
JP3 Installing JP3 and removing JP2, indirectly dc couples
waveform (± 50 mV p-p) can be monitored via test point TP4.
AIN (J1) to the AD1672 analog input via the inverting
JP8 Installing JP8 and removing JP5, JP6 and JP7 selects the
op amp U1.
offset adjustment option. Removing JP8 and connecting
S4 Selects inverting or noninverting gain of one for the am-
plifier U1. When S4 is in position A, the noninverting
E1 to U8 via an external user-supplied ribbon cable
selects the reconstruction option.
mode is selected. When S1 is in position B, the inverting
mode is selected.
REV. 0
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