AD1672_15 Datasheet, PDF (13/20 Pages) Analog Devices – Complete 12-Bit, 3 MSPS Monolithic A/D Converter

AD1672
The power dissipated by the correction logic and output buffers
75
is largely proportional to the clock frequency; running at reduced
clock rates provides a slight reduction in power consumption.
70
Figure 24 illustrates this tradeoff.
65
260
60
258
55
256
254
50
DRV_DD
V_DD
V_CC
252
45
250
40
OBSOLETE 248
246
244
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
FREQUENCY – MHz
Figure 24. Typical Power Dissipation vs. Clock Frequency
GROUNDING AND POWER SUPPLY DECOUPLING
RULES
Proper grounding and decoupling should be a primary design
objective in any high speed, high resolution system. The AD1672
features separate analog and digital supply and ground pins to
optimize the management of analog and digital ground currents
in a system. In general, V_CC, the analog supply, should be de-
coupled to ACOM, the analog common, as close to the chip as
physically possible. Similarly, V_DD, the digital supply, should be
decoupled to DCOM as close to the chip as physically as pos-
0.1
0.2
0.5
1
2
FREQUENCY – MHz
5
10
Figure 26. S/(N+D) vs. Supply Noise Frequency
power supply ripple at various frequencies. Figure 26 shows the
degradation in S/(N+D) ratio resulting from this 100 mV power
supply ripple for a full-scale analog input at 500 kHz. The
AD1672/EB evaluation board was used to generate these graphs
The AD1672 is designed to minimize the code dependent cur-
rent at REFCOM, therefore reducing input dependent analog
ground voltage drops and errors. The majority of code depen-
dent ground current is diverted to ACOM.
The digital activity on the AD1672 chip falls into two general
categories: CMOS correction logic, and CMOS output drivers.
The internal correction logic draws relatively small surges of
current which flow through V_DD and DCOM. The output
drivers draw large current impulses while the output bits are
changing. The size and duration of these currents is a function
sible. DRV_DD, the digital supply for the output drivers should
be decoupled to DRCOM which is also connected to the digital
ground plane.
of the load on the output bits: large capacitive loads are to be
avoided. The output drivers are supplied through DRV_DD and
DRCOM. A 0.1 µF ceramic capacitor for decoupling the driver
Figure 31, the AD1672/EB evaluation board schematic, demon-
supply, DRV_DD, is appropriate for a reasonable capacitive load
on the digital outputs (typically 20 pF on each pin). Applica-
strates the recommended decoupling strategy for the supply
tions involving greater digital loads should consider increasing
pins. Note that in extremely noisy environments, a more elabo- _{the digital decoupling proportionately.}
rate supply filtering scheme may be necessary. Figure 25 shows
the power supply rejection ratio vs. frequency for 100 mV of
For those applications that require a single +5 V supply for both
the analog and digital supply, a clean analog supply may be
–30
generated using the circuit shown in Figure 27. The circuit
–40
–50
V_CC
–60
consists of a differential LC filter with separate power supply
and return lines. Lower noise can be attained using low ESR
(Equivalent Series Resistance) type electrolytic and tantalum
capacitors.
–70
–80
–90
–100
–110
–120
0.1
0.2
V_DD
DRV_DD
0.5
1
2
FREQUENCY – MHz
5
10
TTL/CMOS
LOGIC
CIRCUITS
FERRITE
BEADS
+5V DGND
+5V
POWER SUPPLY
100µF
ELECT.
10–20µF
TANT.
0.1µF
CER.
+5V
AGND
Figure 25. Power Supply Rejection vs. Frequency,
100 mV p-p Signal on Power Supplies
Figure 27. Differential LC Filter for Single +5 V Applications
REV. 0
–13–