OP176 Datasheet, PDF (13/21 Pages) Analog Devices – Bipolar/JFET, Audio Operational Amplifier

OP176
A Low Noise, +5 V/+10 V Reference
In many high resolution applications, voltage reference noise
can be a major contributor to overall system error. Monolithic
voltage references often exhibit too much wide band noise to be
used alone in these systems. Only through careful filtering and
buffering of these monolithic references can one realize wide-
band microvolt noise levels. The circuit illustrated in Figure 41
is an example of a low noise precision reference optimized for
both ac and dc performance around the OP176. With a +10 V
reference (the AD587), the circuit exhibits a 1 kHz spot output
noise spectral density < 10 nV/√Hz. The reference output
voltage is selectable between 5 V and 10 V, depending only on
the selection of the monolithic reference. The output table
illustrated in the figure provides a selection of monolithic
references compatible with this circuit.
V_OUT
10V
10V
10V
10V
5V
5V
5V
5V
OUTPUT TABLE
U1
AD587
REF01
REF10
AD581
REF195
AD586
REF02
REF05
TOLERANCE
(+/–mV)
5 TO 10
30 TO 100
30 TO 50
5 TO 30
2 TO 10
2.5 TO 20
15 TO 50
15 TO 25
+15V
2
6
8
U1 ₅
4
C4
0.1µF
R1
1kΩ
R2
10kΩ
R_TRIM
10kΩ
(OPTIONAL)
R4
100Ω
U2 ₆
OP176
7
4
R3
100Ω
32
C3
100µF/25V
C1
100µF/25V
C2
100µF/25V
R5
1.1kΩ
C5
10µF/25V
V_OUT
R6
3.3Ω
REF
COMMON
A Differential ADC Driver
High performance audio sigma-delta ADCs, such as the stereo
16-bit AD1878 and the 18-bit AD1879, present challenging
design problems with regards to input interfacing. Because of
an internal switched capacitor input circuit, the ADC input
structure presents a difficult dynamic load to the drive amplifier
with fast transient input currents due to their 3 MHz ADC
sampling rate. Also, these ADCs inputs are differential with a
rated full-scale range of ± 6.3 V, or about 4.4 V rms. Hence, the
ADC interface circuit of Figure 42 is designed to accept a
balanced input signal to drive the low dynamic impedances seen
at the inputs of these ADCs. The circuit uses two OP176
TO
U1, U2
C1
100pF
+V_S
0.1µF
–V_S ^0.1µF
R2
R1
ΩR5
+12V
ANALOG
100µ/25V
COM
100µ/25V
–12V
ANALOG
BALANCED
INPUTS
(+)
(–)
5.62kΩ
5.76kΩ 51Ω
U1
U1, U2 = OP176
C2 100pF
R4
R3
ΩR6
C4
0.01µF
C3
0.0047µF
TO
V_IN – AD1878/
AD1879
SIGMA-
DELTA
ADC
V_IN + L & R
INPUTS
5.62kΩ
5.49kΩ 51Ω
U2
C5
0.01µF
= AG, PIN 10 OR 18
(+)
5kΩ _5kΩ
USE
FOR
SINGLE-ENDED
INPUTS
NOTES
C1–C5 = NPO CERAMIC, NON-INDUCTIVE,
C3-C5 CLOSE TO ADC
R1–R6 = 1% METAL FILM
Figure 41. A Low Noise, +5 V/+10 V Reference
In operation, the basic reference voltage is set by U1, either a
5 V or 10 V 3-terminal reference chosen from the table. In this
case, the reference used is a 10 V buried Zener reference, but
all U1 IC types shown can plug into the pinout and can be
optionally trimmed. The stable 10 V from the reference is then
applied to the R1-C1-C2 noise filter, which uses electrolytic
capacitors for a low corner frequency. When electrolytic
capacitors are used for filtering, one must be cognizant of their
dc leakage current errors. Here, however, a dc bootstrap of C1
is used, so this capacitor sees only the small R2 dc drop as bias,
effectively lowering its leakage current to negligible levels. The
resulting low noise, dc-accurate output of the filter is then
buffered by a low noise, unity gain op amp using an OP176.
With the OP176’s low V_OS and control of the source resistances,
the dc performance of this circuit is quite good and will not
compromise voltage reference accuracy and/or drift. Also, the
OP176 has a typical current limit of 50 mA, so it can provide
higher output currents when compared to a typical IC reference
alone.
Figure 42. A Balanced Driver Circuit for Sigma-Delta ADCs
amplifiers as inverting low-pass filters for their speed and high
output current drive. The outputs of the OP176s then drive the
differential ADC inputs through an RC network. This RC
network buffers the amplifiers against step changes at the ADC
sampling inputs using one differential (C3) and two common-
mode connected capacitors (C4 and C5). The 51 Ω series
resistors isolate the OP176s from the heavily capacitive loads,
while the capacitors absorb the transient currents. Operating on
± 12 V supplies, this circuit exhibits a very low THD + N of
0.001% at 5 V rms outputs. For single-ended drive sources, a
third op amp unity gain inverter can be added between R2’s (+)
input terminal and R4. For best results, short-lead, noninduc-
tive capacitors are suggested for C3, C4, and C5 (which are
placed close to the ADC), and 1% metal-film types for R1
through R6. For surface mount PCBs, these components can
be NPO ceramic chip capacitors and thin-film chip resistors.
REV. 0
–13–