OP467 Datasheet, PDF (11/16 Pages) Analog Devices – Quad Precision, High Speed Operational Amplifier

OP467
APPLICATIONS INFORMATION
OUTPUT SHORT-CIRCUIT PERFORMANCE
To achieve a wide bandwidth and high slew rate, the OP467
output is not short circuit protected. Shorting the output to
ground or to the supplies may destroy the device.
For safe operation, the output load current should be limited so
that the junction temperature does not exceed the absolute
maximum junction temperature.
To calculate the maximum internal power dissipation, the fol-
lowing formula can be used:
P_D
= ^TJ
max– T_A
θ_JA
where T_J and T_A are junction and ambient temperatures respec-
tively, P_D is device internal power dissipation, and θ_JA is pack-
aged device thermal resistance given in the data sheet.
UNUSED AMPLIFIERS
It is recommended that any unused amplifiers in a quad package
be connected as a unity gain follower with a 1 kΩ feedback
resistor with noninverting input tied to the ground plain.
PRINTED CIRCUIT BOARD LAYOUT
CONSIDERATIONS
Satisfactory performance of a high speed op amp largely depends
on a good PC layout. To achieve the best dynamic performance,
following high frequency layout technique is recommended.
GROUNDING
A good ground plain is essential to achieve the optimum perfor-
mance in high speed applications. It can significantly reduce the
undesirable effects of ground loops and IR drops by providing a
low impedance reference point. Best results are obtained with a
multilayer board design with one layer assigned to ground plain.
To maintain a continuous and low impedance ground, avoid
running any traces on this layer.
POWER SUPPLY CONSIDERATIONS
In high frequency circuits, device lead length introduces an
inductance in series with the circuit. This inductance, combined
with stray capacitance, forms a high frequency resonance circuit.
Poles generated by these circuits will cause gain peaking and
additional phase shift, reducing the op amp’s phase margin and
leading to an unstable operation.
A practical solution to this problem is to reduce the resonance
frequency low enough to take advantage of the amplifier’s power
supply rejection.
This is easily done by placing capacitors across the supply line
and the ground plain as close as possible to the device pin. Since
capacitors also have internal parasitic components, such as stray
inductance, selecting the right capacitor is important. To be
effective, they should have low impedance over the frequency
range of interest. Tantalum capacitors are an excellent choice
for their high capacitance/size ratio, but their ESR (Effective
Series Resistance) increases with frequency making them less
effective. On the other hand, ceramic chip capacitors have excel-
lent ESR and ESL (Effective Series Inductance) performance at
higher frequencies, and because of their small size, they can be
placed very close to the device pin, further reducing the stray
inductance. Best results are achieved by using a combination of
these two capacitors. A 5 µF–10 µF tantalum parallel with a
0.1 µF ceramic chip caps are recommended. If additional isola-
tion from high frequency resonances of the power supply is
needed, a ferrite bead should be placed in series with the supply
lines between the bypass caps and the power supply. A word of
caution, addition of the ferrite bead will introduce a new pole
and zero to frequency response of the circuit and could cause
unstable operation if it is not selected properly.
+V_S
+
10␮F TANTALUM
0.1␮F CERAMIC CHIP
0.1␮F CERAMIC CHIP
–
10␮F TANTALUM
–V_S
Figure 36. Recommended Power Supply Bypass
SIGNAL CONSIDERATIONS
Input and output traces need special attention to assure a mini-
mum stray capacitance. Input nodes are very sensitive to capaci-
tive reactance, particularly when connected to a high impedance
circuit. Stray capacitance can inject undesirable signals from a
noisy line into a high impedance input. Protect high impedance
input traces by providing guard traces around them. This will
also improve the channel separation significantly.
Additionally, any stray capacitance in parallel with the op amp’s
input capacitance generates a pole in the frequency response of
the circuit. The additional phase shift caused by this pole will
reduce the circuit’s gain margin. If this pole is within the gain
range of the op amp, it will cause unstable performance. To
reduce these undesirable effects, use the lowest impedance
where possible. Lowering the impedance at this node places the
poles at a higher frequency, far above the gain range of the am-
plifier. Stray capacitance on the PC board can be reduced by
making the traces narrow and as short as possible. Further re-
duction can be realized by choosing smaller pad size, increasing
the spacing between the traces, and using PC board material
with a low dielectric constant insulator (Dielectric Constant of
some common insulators: air = 1, Teflon^® = 2.2, and FR4 =
4.7; with air being an ideal insulator).
Removing segments of the ground plain directly under the input
and output pads is recommended.
Outputs of high speed amplifiers are very sensitive to capacitive
loads. A capacitive load will introduce a pair of pole and zero to
the circuit’s frequency response, reducing the phase margin,
leading to unstable operation or oscillation.
Teflon is a registered trademark of E.I. du Pont Co.
REV. C
–11–