ADSP-21161N Datasheet, PDF (11/60 Pages) Analog Devices – DSP Microcomputer

ADSP-21161N
1
GND
3
KEY (NO PIN)
5
BTMS
7
BTCK
BTRST
BTDI
9
9
11
2
EMU
4
GND
6
TMS
8
TCK
10
TRST
12
TDI
13
GND
14
TDO
0.64"
0.88"
0.24"
Figure 8. JTAG Pod Connector Dimensions
TOP VIEW
0 .10 "
Figure 7. JTAG Target Board Connector with No
Local Boundary Scan
JTAG Emulator Pod Connector
Figure 8 details the dimensions of the JTAG pod connector at the
14-pin target end. Figure 9 displays the keep-out area for a target
board header. The keep-out area enables the pod connector to
properly seat onto the target board header. This board area
should contain no components (chips, resistors, capacitors, etc.).
The dimensions are referenced to the center of the 0.025" square
post pin.
Design-for-Emulation Circuit Information
For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan chains,
signal buffering, signal termination, and emulator pod logic, see
0.1 5"
Figure 9. JTAG Pod Connector Keep-Out Area
the EE-68: Analog Devices JTAG Emulation Technical Reference on
the Analog Devices website (www.analog.com)—use site search
on “EE-68”. This document is updated regularly to keep pace
with improvements to emulator support.
Additional Information
This data sheet provides a general overview of the ADSP-21161N
architecture and functionality. For detailed information on the
ADSP-2116x Family core architecture and instruction set, refer
to the ADSP-21161 SHARC DSP Hardware Reference and the
ADSP-21160 SHARC DSP Instruction Set Reference.
REV. A
–11–