ADSP-21161N Datasheet, PDF (1/60 Pages) Analog Devices – DSP Microcomputer

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DSP Microcomputer
ADSP-21161N
SUMMARY
High Performance 32-Bit DSP—Applications in Audio,
Medical, Military, Wireless Communications,
Graphics, Imaging, Motor-Control, and Telephony
Super Harvard Architecture—Four Independent Buses
for Dual Data Fetch, Instruction Fetch, and
Nonintrusive, Zero-Overhead I/O
Code Compatible with All Other SHARC Family DSPs
Single-Instruction-Multiple-Data (SIMD) Computational
Architecture—Two 32-Bit IEEE Floating-Point
Computation Units, Each with a Multiplier, ALU,
Shifter, and Register File
Serial Ports Offer I²S Support Via 8 Programmable and
Simultaneous Receive or Transmit Pins, which
Support up to 16 Transmit or 16 Receive Channels of
Audio
Integrated Peripherals—Integrated I/O Processor,
1M Bit On-Chip Dual-Ported SRAM, SDRAM
Controller, Glueless Multiprocessing Features, and
I/O Ports (Serial, Link, External Bus, SPI, and JTAG)
ADSP-21161N Supports 32-Bit Fixed, 32-Bit Float, and
40-Bit Floating-Point Formats
KEY FEATURES
100 MHz (10 ns) Core Instruction Rate
Single-Cycle Instruction Execution, Including SIMD
Operations in Both Computational Units
600 MFLOPs Peak and 400 MFLOPs Sustained
Performance
225-Ball 17 mm × 17 mm MBGA Package
FUNCTIONAL BLOCK DIAGRAM
CORE PROCESSOR
TIMER
INSTRUCTION
CACHE
32 ؋ 48-BIT
DAG1
DAG2
8 ؋ 4 ؋ 32 8 ؋ 4 ؋ 32
PROGRAM
SEQUENCER
BUS
CONNECT
(PX)
32
PM ADDRESS BUS
32
DM ADDRESS BUS
64
PM DATA BUS
64
DM DATA BUS
DUAL-PORTED SRAM
TWO INDEPENDENT
DUAL-PORTED BLOCKS
PROCESSOR PORT
I/O PORT
ADDR
DATA
DATA
ADDR
ADDR
DATA
DATA
ADDR
IOD
IOA
64
18
MULT
DATA
REGISTER
FILE
(PEX)
16 ؋ 40-BIT
BARREL
SHIFTER
BARREL
SHIFTER
DATA
REGISTER
FILE
(PEY)
16 ؋ 40-BIT
MULT
JTAG TEST
6
AND EMULATION
GPIO
12
FLAGS
8
SDRAM
CONTROLLER
EXTERNAL PORT
ADDR BUS
24
MUX
MULTIPROCESSOR
INTERFACE
DATA BUS
32
MUX
HOST PORT
ALU
ALU
DMA
5
IOP
CONTROLLER
REGISTERS
(MEMORY MAPPED)
SERIAL PORTS (4)
16
CONTROL,
STATUS, &
DATA BUFFERS
20
LINK PORTS (2)
4
SPI PORTS (1)
I/O PROCESSOR
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