ADSP-TS201S_06 Datasheet, PDF (1/48 Pages) Analog Devices – TigerSHARC-R Embedded Processor

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TigerSHARC^®
Embedded Processor
ADSP-TS201S
KEY FEATURES
Up to 600 MHz, 1.67 ns instruction cycle rate
24M bits of internal—on-chip—DRAM memory
25 mm × 25 mm (576-ball) thermally enhanced ball grid
array package
Dual-computation blocks—each containing an ALU, a
multiplier, a shifter, a register file, and a communications
logic unit (CLU)
Dual-integer ALUs, providing data addressing and pointer
manipulation
Integrated I/O includes 14-channel DMA controller, external
port, four link ports, SDRAM controller, programmable
flag pins, two timers, and timer expired pin for system
integration
1149.1 IEEE-compliant JTAG test access port for on-chip
emulation
Single-precision IEEE 32-bit and extended-precision 40-bit
floating-point data formats and 8-, 16-, 32-, and 64-bit
fixed-point data formats
KEY BENEFITS
Provides high performance static superscalar DSP
operations, optimized for telecommunications
infrastructure and other large, demanding multiprocessor
DSP applications
Performs exceptionally well on DSP algorithm and I/O
benchmarks (see benchmarks in Table 1)
Supports low overhead DMA transfers between internal
memory, external memory, memory-mapped peripherals,
link ports, host processors, and other
(multiprocessor) DSPs
Eases DSP programming through extremely flexible instruc-
tion set and high-level-language-friendly DSP architecture
Enables scalable multiprocessing systems with low commu-
nications overhead
Provides on-chip arbitration for glueless multiprocessing
DATA ADDRESS GENERATION
INTEGER ³²
32
INTEGER
J ALU
K ALU
PROGRAM
SEQUENCER
ADDR
FETCH
32-BIT × 32-BIT
J-BUS ADDR
J-BUS DATA
32-BIT × 32-BIT
BTB
K-BUS ADDR
K-BUS DATA
I-BUS ADDR
PC
I-BUS DATA
IAB
T
24M BITS INTERNAL MEMORY
MEMORY BLOCKS
(PAGE CACHE)
4 × CROSSBAR CONNECT
32 ^{A D A D A D A D}
128
32
128
32
SOC
I/F
128
S-BUS ADDR
21
S-BUS DATA 128
CLU
SHIFT
128
X
ALU MUL
REGISTER
FILE
128
32-BIT × 32-BIT
DAB
DAB
128
Y
128
REGISTER
FILE
MUL ALU SHIFT
32-BIT × 32-BIT
SOC BUS
JTAG PORT
6
JTAG
EXTERNAL
PORT
HOST
32
ADDR
MULTI-
PROC
64
DATA
SDRAM ⁸
CTRL
CTRL
C-BUS ¹⁰ _CTRL
ARB
CLU
EXT DMA
REQ 4
DMA
LINK PORTS
4
IN 8
L0
4
OUT 8
4
IN 8
L1
4
OUT 8
4
IN 8
L2
4
OUT 8
4
IN 8
L3
4
OUT 8
COMPUTATIONAL BLOCKS
Figure 1. Functional Block Diagram
TigerSHARC and the TigerSHARC logo are registered trademarks of Analog Devices, Inc.
Rev. C
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