ADSP-2185M Datasheet, PDF (1/40 Pages) Analog Devices – DSP Microcomputer

a
DSP
Microcomputer
ADSP-2185M
FEATURES
Performance
13.3 ns Instruction Cycle Time @ 2.5 V (Internal),
75 MIPS Sustained Performance
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in
Every Instruction Cycle
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby Power
Dissipation with 200 CLKIN Cycle Recovery from
Power-Down Condition
Low Power Dissipation in Idle Mode
Integration
ADSP-2100 Family Code Compatible (Easy to Use
Algebraic Syntax), with Instruction Set Extensions
80K Bytes of On-Chip RAM, Configured as
16K Words Program Memory RAM
16K Words Data Memory RAM
Dual-Purpose Program Memory for Both Instruction and
Data Storage
Independent ALU, Multiplier/Accumulator, and Barrel
Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides Zero Overhead
Looping Conditional Instruction Execution
Programmable 16-Bit Interval Timer with Prescaler
100-Lead LQFP and 144-Ball Mini-BGA
System Interface
Flexible I/O Structure Allows 2.5 V or 3.3 V Operation;
All Inputs Tolerate up to 3.6 V Regardless of Mode
16-Bit Internal DMA Port for High-Speed Access to
On-Chip Memory (Mode Selectable)
4 MByte Memory Interface for Storage of Data Tables
and Program Overlays (Mode Selectable)
8-Bit DMA to Byte Memory for Transparent Program
and Data Memory Transfers (Mode Selectable)
I/O Memory Interface with 2048 Locations Supports
Parallel Peripherals (Mode Selectable)
Programmable Memory Strobe and Separate I/O
Memory Space Permits “Glueless” System Design
Programmable Wait State Generation
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Automatic Booting of On-Chip Program Memory from
Byte-Wide External Memory, e.g., EPROM, or
through Internal DMA Port
Six External Interrupts
13 Programmable Flag Pins Provide Flexible System
Signaling
UART Emulation through Software SPORT Reconfiguration
ICE-Port™ Emulator Interface Supports Debugging in
Final Systems
FUNCTIONAL BLOCK DIAGRAM
DATA ADDRESS
GENERATORS
DAG1 DAG2
PROGRAM
SEQUENCER
POWER-DOWN
CONTROL
MEMORY
PROGRAM
MEMORY
16K ؋ 24 BIT
DATA
MEMORY
16K ؋ 16 BIT
PROGRAMMABLE
I/O
AND
FLAGS
PROGRAM MEMORY ADDRESS
FULL MEMORY MODE
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
ARITHMETIC UNITS
ALU
MAC SHIFTER
ADSP-2100 BASE
ARCHITECTURE
ICE-Port is a trademark of Analog Devices, Inc.
REV. 0
SERIAL PORTS
SPORT0 SPORT1
TIMER
BYTE DMA
CONTROLLER
OR
EXTERNAL
DATA
BUS
INTERNAL
DMA
PORT
HOST MODE
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© Analog Devices, Inc., 2000