PAC5220 Datasheet, PDF (55/73 Pages) Active-Semi, Inc – Power Application Controller

PAC5220
Power Application Controller
16.3. Functional Description
The ARM Cortex-M0 microcontroller core is configured for little endian operation and includes the fast
single-cycle 32-bit multiplier and 24-bit SysTick timer and can operate at a frequency of up to 50MHz.
The microcontroller nested vectored interrupt controller (NVIC) supports 25 external interrupts for the device's
peripherals and sub-systems. For low-latency interrupt processing, the NVIC also supports interrupt tail-
chaining. The wake-up interrupt controller (WIC) is able to wake up the device from low-power modes using any
GPIO interrupt, as well as from the RTC or WDT. The ARM Cortex-M0 supports both sleep and deep-sleep low-
power modes. The deep-sleep mode supports clock gating to limit standby power even further.
Firmware debug support includes 4 break-point and 2 watch-point unit comparators using the serial wire debug
(SWD) protocol. The serial wire debug mechanism can be disabled to prevent device access to the firmware in
the field.
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Rev 1.0‒February 25, 2014