PAC5220 Datasheet, PDF (40/73 Pages) Active-Semi, Inc – Power Application Controller

Table 12-2. Microcontroller Port and PWM to Power Driver Mapping
PART
NUMBER
PWMA0
PWMA1
PWMA2
PWMA3/
PWMA4/
PWMB0
PAC5220
DRL0
DRL1
DRL2
DRH3
PAC5220
Power Application Controller
PWMA5/
PWMC0
DRH4
PWMA6/
PWMD0
DRH5
Table 12-3. Power Driver Delay Configuration
DELAY
SETTING
RISING
DRLx
FALLING
00b Default Setting
130ns
140ns
01b Setting
170ns
180ns
10b Setting
230ns
250ns
11b Setting
360ns
380ns
RISING
160ns
200ns
260ns
380ns
DRHx
FALLING
140ns
180ns
240ns
370ns
12.3.6. Gate Driver Fault Protection
The ASPD incorporates a configurable fault protection mechanism using protection signal from the Configurable
Analog Front End (CAFE), designated as protection event 1 (PR1) signal. The DRL0/DRL1/DRL2 drivers are
designated as low-side group 1. The DRH3/DRH4/DRH5 gate drivers are designated as high-side group 1. The
PR1 signal from the CAFE can be used to disable low-side group 1, high-side group 1, or both depending on the
PR1 mask bit settings.
- 40 -
Rev 1.0‒February 25, 2014