EVK-ACT8945AQJ303-T Datasheet, PDF (28/42 Pages) Active-Semi, Inc – Advanced PMU for Atmel SAMA5D3 Series & SAM9 Series Processors

ACT8945A
Rev 2, 11-Feb-14
PWRHLD) before nPBIN is de-asserted. If the
microprocessor is unable to complete its power-up
routine successfully before the user releases the
push-button, the ACT8945A automatically shuts the
system down. This provides protection against
accidental or momentary assertions of the push-
button. If desired, longer “push-and-hold” times can
be implemented by simply adding an additional time
delay before asserting PWRHLD.
Control Sequences
The ACT8945A features a variety of control
sequences that are optimized for supporting system
enable and disable sequences of Atmel SAMA5D3
series and SAM9 series application processors.
Enabling/Disabling Sequence
ACT8945AQJ303 Sequence
A typical enable sequence is initiated whenever
nPBIN is asserted low via 50KΩ resistance. The
enable sequence begins by enabling REG3. When
REG3 reaches its power-OK threshold, nRSTO is
asserted low, resetting the microprocessor. When
REG3 reaches its power-OK threshold for 2ms ,
REG1 is enabled. When REG3 reaches its power-
OK threshold for 4ms , REG2 is enabled. When
REG3 is above its power-OK threshold when the
reset timer expires, nRSTO is de-asserted, allowing
the microprocessor to begin its boot sequence.
REG4, REG5, REG6 and REG7 can be enabled or
disabled by PWREN after system powers up.
During the boot sequence, the microprocessor must
assert PWRHLD, holding the regulators to ensure
that the system remains powered after nPBIN is
released.
As with the enable sequence, a typical disable
sequence is initiated when the user presses the
push-button, which interrupts the processor via the
nPBSTAT output. The actual disable sequence is
completely software-controlled, but typically
involved initiating various “clean-up” processes
before finally set MSTROFF[ ] bit to 1 to shut the
system down.
Figure 3:
ACT8945AQJ303 Enable/Disable Sequence
1
: Typical value shown, actual delay time may vary from (T-1ms) x 88% to T x 112%, where T is the typical delay time setting.
Innovative Power^TM
- 28 -
Active-Semi Proprietary―For Authorized Recipients and Customers
ActivePMU^TM and ActivePath^TM are trademarks of Active-Semi.
I²C^TM is a trademark of NXP.
www.active-semi.com
Copyright © 2014 Active-Semi, Inc.