EVK-ACT8945AQJ303-T Datasheet, PDF (10/42 Pages) Active-Semi, Inc – Advanced PMU for Atmel SAMA5D3 Series & SAM9 Series Processors

REGISTER AND BIT DESCRIPTIONS
Table 1:
Global Register Map
ACT8945A
Rev 2, 11-Feb-14
OUTPUT ADDRESS BIT NAME ACCESS
DESCRIPTION
SYS
0x00 [7]
TRST
Reset Timer Setting. Defines the reset time-out threshold. Reset
R/W time-out is 65ms when value is 1, reset time-out is 260ms when
value is 0. See nRSTO Output section for more information.
SYS
SYS
0x00
0x00
[6] nSYSMODE R/W
[5] nSYSLEVMSK R/W
SYSLEV Mode Select. Defines the response to the SYSLEV
voltage detector, 1: Generate an interrupt when V_VSYS falls below
the programmed SYSLEV threshold, 0: automatic shutdown
when V_VSYS falls below the programmed SYSLEV threshold.
System Voltage Level Interrupt Mask. SYSLEV interrupt is
masked by default, set to 1 to unmask this interrupt. See the
Programmable System Voltage Monitor section for more
information
SYS
0x00 [4] nSYSSTAT
System Voltage Status. Value is 1 when V_VSYS is lower than the
R SYSLEV voltage threshold, value is 0 when V_VSYS is higher than
the system voltage detection threshold.
SYS
0x00 [3:0] SYSLEV
System Voltage Detect Threshold. Defines the SYSLEV voltage
R/W threshold. See the Programmable System Voltage Monitor
section for more information.
SYS
0x01 [7:6]
-
R/W Reserved.
SYS
0x01
[5] MSTROFF
R/W
Master Off Control. Set bit to 1 to turn off all regulators. The bit
will be automatically cleared to 0 when nPBIN is asserted.
SYS
SYS
REG1
REG1
REG1
REG1
REG1
REG1
REG1
REG1
REG1
REG1
0x01 [4]
-
0x01 [3:0] SCRATCH
0x20 [7:6]
-
0x20 [5:0] VSET1
0x21 [7:6]
-
0x21 [5:0] VSET2
0x22 [7]
ON
0x22 [6] PHASE
0x22 [5]
MODE
0x22 [4:2] DELAY
0x22 [1] nFLTMSK
0x22 [0]
OK
R/W Reserved.
Scratchpad Bits. Non-functional bits, maybe be used by user to
R/W store system status information. Volatile bits, which are cleared
when system voltage falls below UVLO threshold.
R Reserved.
Primary Output Voltage Selection. Valid when VSEL is driven low.
R/W See the Output Voltage Programming section for more
information.
R Reserved.
Secondary Output Voltage Selection. Valid when VSEL is driven
R/W high. See the Output Voltage Programming section for more
information.
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear bit
to 0 to disable the regulator.
Regulator Phase Control. Set bit to 1 for the regulator to operate
R/W 180° out of phase with the oscillator, clear bit to 0 for the
regulator to operate in phase with the oscillator.
Regulator Mode Select. Set bit to 1 for fixed-frequency PWM
R/W under all load conditions, clear bit to 0 to transit to power-savings
mode under light-load conditions.
R/W
Regulator Turn-On Delay Control. See the REG1, REG2, REG3
Turn-on Delay section for more information.
R/W
Regulator Fault Mask Control. Set bit to 1 enable fault-interrupts,
clear bit to 0 to disable fault-interrupts.
R
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
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