U1AFS600-FGG256I Datasheet, PDF (8/17 Pages) Actel Corporation – Actel Fusion Mixed-Signal FPGA

Fusion Device Family Overview
Advanced Flash Technology
The Fusion family offers many benefits, including nonvolatility and reprogrammability through an
advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design
techniques are used to implement logic and control functions. The combination of fine granularity,
enhanced flexible routing resources, and abundant flash switches allows very high logic utilization
(much higher than competing SRAM technologies) without compromising device routability or
performance. Logic functions within the device are interconnected through a four-level routing
hierarchy.
Advanced Architecture
The proprietary Fusion architecture provides granularity comparable to standard-cell ASICs. The
Fusion device consists of several distinct and programmable architectural features, including the
following (Figure 1-1 on page 1-6):
• Embedded memories
– Flash memory blocks
– FlashROM
– SRAM and FIFO
• Clocking resources
– PLL and CCC
– RC oscillator
– Crystal oscillator
– No-Glitch MUX (NGMUX)
• Digital I/Os with advanced I/O standards
• FPGA VersaTiles
• Analog components
– ADC
– Analog I/Os supporting voltage, current, and temperature monitoring
– 1.5 V on-board voltage regulator
– Real-time counter
The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input
logic lookup table (LUT) equivalent or a D-flip-flop or latch (with or without enable) by
programming the appropriate flash switch interconnections. This versatility allows efficient use of
the FPGA fabric. The VersaTile capability is unique to the Actel families of flash-based FPGAs.
VersaTiles and larger functions are connected with any of the four levels of routing hierarchy. Flash
switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect
programming. Maximum core utilization is possible for virtually any design.
In addition, extensive on-chip programming circuitry allows for rapid (3.3 V) single-voltage
programming of Fusion devices via an IEEE 1532 JTAG interface.
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