U1AFS600-FGG256I Datasheet, PDF (13/17 Pages) Actel Corporation – Actel Fusion Mixed-Signal FPGA

Actel Fusion Mixed-Signal FPGAs for the MicroBlade AdvancedMC Solution
Digital I/Os with Advanced I/O Standards
The Fusion family of FPGAs features a flexible digital I/O structure, supporting a range of voltages
(1.5 V, 1.8 V, 2.5 V, and 3.3 V). Fusion FPGAs support many different digital I/O standards, both
single-ended and differential.
The I/Os are organized into banks, with four or five banks per device. The configuration of these
banks determines the I/O standards supported. The banks along the east and west sides of the
device support the full range of I/O standards (single-ended and differential). The south bank
supports the Analog Quads (analog I/O). In the family's two smaller devices, the north bank
supports multiple single-ended digital I/O standards. In the family’s larger devices, the north bank is
divided into two banks of digital Pro I/Os, supporting a wide variety of single-ended, differential,
and voltage-referenced I/O standards.
Each I/O module contains several input, output, and enable registers. These registers allow the
implementation of the following applications:
• Single-Data-Rate (SDR) applications
• Double-Data-Rate (DDR) applications—DDR LVDS I/O for chip-to-chip communications
• Fusion banks support LVPECL, LVDS, BLVDS, and M-LVDS with 20 multi-drop points.
VersaTiles
The Fusion core consists of VersaTiles, which are also used in the successful Actel ProASIC3 family.
The Fusion VersaTile supports the following:
• All 3-input logic functions—LUT-3 equivalent
• Latch with clear or set
• D-flip-flop with clear or set and optional enable
Refer to Figure 1-2 for the VersaTile configuration arrangement.
LUT-3 Equivalent D-Flip-Flop with Clear or Set Enable D-Flip-Flop with Clear or Set
X1
X2 LUT-3 Y
X3
Data
CLK
CLR
Y
D-FF
Figure 1-2 • VersaTile Configurations
Data
CLK
Y
D-FFE
Enable
CLR
Preliminary v0.4
1-9