U1AFS600-FGG256I Datasheet, PDF (12/17 Pages) Actel Corporation – Actel Fusion Mixed-Signal FPGA

Fusion Device Family Overview
(AEMPTY) and Almost Full (AFULL) flags in addition to the normal EMPTY and FULL flags. The
embedded FIFO control unit contains the counters necessary for the generation of the read and
write address pointers. The SRAM/FIFO blocks can be cascaded to create larger configurations.
Clock Resources
PLLs and Clock Conditioning Circuits (CCCs)
Fusion devices provide designers with very flexible clock conditioning capabilities. Each member of
the Fusion family contains six CCCs. In the two larger family members, two of these CCCs also
include a PLL; the smaller devices support one PLL.
The inputs of the CCC blocks are accessible from the FPGA core or from one of several inputs with
dedicated CCC block connections.
The CCC block has the following key features:
• Wide input frequency range (f_{IN_CCC}) = 1.5 MHz to 350 MHz
• Output frequency range (f_{OUT_CCC}) = 0.75 MHz to 350 MHz
• Clock phase adjustment via programmable and fixed delays from –6.275 ns to +8.75 ns
• Clock skew minimization (PLL)
• Clock frequency synthesis (PLL)
• On-chip analog clocking resources usable as inputs:
– 100 MHz on-chip RC oscillator
– Crystal oscillator
Additional CCC specifications:
• Internal phase shift = 0°, 90°, 180°, and 270°
• Output duty cycle = 50% ± 1.5%
• Low output jitter. Samples of peak-to-peak period jitter when a single global network is
used:
– 70 ps at 350 MHz
– 90 ps at 100 MHz
– 180 ps at 24 MHz
– Worst case < 2.5% × clock period
• Maximum acquisition time = 150 µs
• Low power consumption of 5 mW
Global Clocking
Fusion devices have extensive support for multiple clocking domains. In addition to the CCC and
PLL support described above, there are on-chip oscillators as well as a comprehensive global clock
distribution network.
The integrated RC oscillator generates a 100 MHz clock. It is used internally to provide a known
clock source to the flash memory read and write control. It can also be used as a source for the PLLs.
The crystal oscillator supports the following operating modes:
• Crystal (32.768 kHz to 20 MHz)
• Ceramic (500 kHz to 8 MHz)
• RC (32.768 kHz to 4 MHz)
Each VersaTile input and output port has access to nine VersaNets: six main and three quadrant
global networks. The VersaNets can be driven by the CCC or directly accessed from the core via
MUXes. The VersaNets can be used to distribute low-skew clock signals or for rapid distribution of
high-fanout nets.
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