A54SX08A-FTQ144 Datasheet, PDF (72/108 Pages) Actel Corporation – SX-A Family FPGAs

SX-A Family FPGAs
Table 2-41 • A54SX72A Timing Characteristics
(Worst-Case Commercial Conditions V_CCA = 2.25 V, V_CCI = 4.75 V, T_J = 70°C)
–3 Speed¹ –2 Speed –1 Speed
Std. Speed
–F Speed
Parameter
Description
5 V PCI Output Module Timing²
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
t_DLH
Data-to-Pad Low to High
t_DHL
Data-to-Pad High to Low
t_ENZL
Enable-to-Pad, Z to L
t_ENZH
Enable-to-Pad, Z to H
t_ENLZ
Enable-to-Pad, L to Z
t_ENHZ
Enable-to-Pad, H to Z
d_TLH3
Delta Low to High
d_THL3
Delta High to Low
5 V TTL Output Module Timing⁴
2.7
3.4
1.3
2.7
3.0
3.4
0.016
0.026
3.1
3.9
1.5
3.1
3.5
3.9
0.016
0.03
3.5
4.4
1.7
3.5
3.9
4.4
0.02
0.032
4.1
5.1
2.0
4.1
4.6
5.1
0.022
0.04
5.7 ns
7.2 ns
2.8 ns
5.7 ns
6.4 ns
7.2 ns
0.032 ns/pF
0.052 ns/pF
t_DLH
Data-to-Pad Low to High
2.4
2.8
3.1
3.7
5.1 ns
t_DHL
Data-to-Pad High to Low
3.1
3.5
4.0
4.7
6.6 ns
t_DHLS
Data-to-Pad High to Low—low slew
7.4
8.5
9.7
11.4
15.9 ns
t_ENZL
Enable-to-Pad, Z to L
2.1
2.4
2.7
3.2
4.5 ns
t_ENZLS
Enable-to-Pad, Z to L—low slew
7.4
8.4
9.5
11.0
15.4 ns
t_ENZH
Enable-to-Pad, Z to H
2.4
2.8
3.1
3.7
5.1 ns
t_ENLZ
Enable-to-Pad, L to Z
3.6
4.2
4.7
5.6
7.8 ns
t_ENHZ
d_TLH3
d_THL3
d_THLS3
Enable-to-Pad, H to Z
Delta Low to High
Delta High to Low
Delta High to Low—low slew
3.1
0.014
0.023
0.043
3.5
0.017
0.029
0.046
4.0
0.017
0.031
0.057
4.7
0.023
0.037
0.066
6.6 ns
0.031 ns/pF
0.051 ns/pF
0.089 ns/pF
Notes:
1. All –3 speed grades have been discontinued.
2. Delays based on 50 pF loading.
3. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the V_CCI value into the following equation:
Slew Rate [V/ns] = (0.1*V_CCI – 0.9*V_CCI)/ (C_load * d_T[LH|HL|HLS])
where C_load is the load capacitance driven by the I/O in pF
d_T[LH|HL|HLS] is the worst case delta value from the datasheet in ns/pF.
4. Delays based on 35 pF loading.
2-52
v5.3