A54SX08A-FTQ144 Datasheet, PDF (39/108 Pages) Actel Corporation – SX-A Family FPGAs

SX-A Family FPGAs
Table 2-14 • A54SX08A Timing Characteristics (Continued)
(Worst-Case Commercial Conditions, V_CCA = 2.25 V_, V_CCI = 3.0 V, T_J = 70°C)
–2 Speed –1 Speed
Std. Speed
–F Speed
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Units
t_INYH
Input Data Pad to Y High 5 V PCI
t_INYL
Input Data Pad to Y Low 5 V PCI
t_INYH
Input Data Pad to Y High 5 V TTL
t_INYL
Input Data Pad to Y Low 5 V TTL
Input Module Predicted Routing Delays²
0.5
0.6
0.8
0.9
0.5
0.6
0.8
0.9
0.7
0.9 ns
1.1
1.5 ns
0.7
0.9 ns
1.1
1.5 ns
t_IRD1
FO = 1 Routing Delay
0.3
0.3
0.4
0.6 ns
t_IRD2
FO = 2 Routing Delay
0.5
0.5
0.6
0.8 ns
t_IRD3
FO = 3 Routing Delay
0.6
0.7
0.8
1.1 ns
t_IRD4
FO = 4 Routing Delay
0.8
0.9
1
1.4 ns
t_IRD8
FO = 8 Routing Delay
1.4
1.5
1.8
2.5 ns
t_IRD12
FO = 12 Routing Delay
2
2.2
2.6
3.6 ns
Notes:
1. For dual-module macros, use t_PD + t_RD1 + t_PDn , t_RCO + t_RD1 + t_PDn , or t_PD1 + t_RD1 + t_SUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
v5.3
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