A54SX08A-FTQ144 Datasheet, PDF (36/108 Pages) Actel Corporation – SX-A Family FPGAs

SX-A Family FPGAs
Input Buffer Delays
PAD
Y
INBUF
In
Out
GND
3V
1.5 V 1.5 V
V_CC
50%
0V
50%
t_INY
t_INY
Figure 2-6 • Input Buffer Delays
Cell Timing Characteristics
C-Cell Delays
S
AY
B
S, A, or B
Out
GND
Out
V_CC
50% 50%
V_CC
50%
GND
50%
t_PD
50%
t_PD
t_PD
GND
t_PD
V_CC
50%
Figure 2-7 • C-Cell Delays
D
CLK
t_SUD
Q
CLR
PRESET
D _{PRESET Q}
CLK
CLR
(Positive Edge Triggered)
t _HD
tt^HRPPWWHH
t_RCO
tt_HRPPWWLL
t_HP
t_CLR
t_WASYN
t_PRESET
Figure 2-8 • Flip-Flops
2-16
v5.3