A42MX16-1PQ100ES Datasheet, PDF (66/123 Pages) Actel Corporation – 40MX and 42MX FPGA Families

40MX and 42MX FPGA Families
Table 35 •
A42MX16 Timing Characteristics (Nominal 3.3V Operation) (Continued)
(Worst-Case Commercial Conditions, V_CCA = 3.0V, T_J = 70°C)
‘–3’ Speed ‘–2’ Speed ‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Input Module Propagation Delays
t_INYH
Pad-to-Y HIGH
t_INYL
Pad-to-Y LOW
t_INGH
G to Y HIGH
t_INGL
G to Y LOW
Input Module Predicted Routing Delays²
1.5
1.6
1.9
2.2
3.1 ns
1.1
1.3
1.4
1.7
2.4 ns
2.0
2.2
2.5
2.9
4.1 ns
2.0
2.2
2.5
2.9
4.1 ns
t_IRD1
FO=1 Routing Delay
t_IRD2
FO=2 Routing Delay
t_IRD3
FO=3 Routing Delay
t_IRD4
FO=4 Routing Delay
t_IRD8
FO=8 Routing Delay
Global Clock Network
2.6
2.9
3.2
3.8
5.3 ns
2.9
3.2
3.7
4.3
6.1 ns
3.3
3.6
4.1
4.9
6.8 ns
3.6
4.0
4.6
5.4
7.6 ns
5.1
5.6
6.4
7.5
10.5 ns
t_CKH
Input LOW to HIGH FO = 32
4.4
4.8
5.5
6.5
9.0 ns
FO = 384
4.8
5.3
6.0
7.1
9.9 ns
t_CKL
Input HIGH to LOW FO = 32
5.3
5.9
6.7
7.8
11.0 ns
FO = 384
6.2
6.9
7.9
9.2
12.9 ns
t_PWH
Minimum Pulse
FO = 32 5.7
6.3
7.1
8.4
11.8
ns
Width HIGH
FO = 384 6.6
7.4
8.3
9.8
13.7
ns
t_PWL
Minimum Pulse
FO = 32 5.3
5.9
6.7
7.8
11.0
ns
Width LOW
FO = 384 6.2
6.9
7.9
9.2
12.9
ns
t_CKSW
Maximum Skew
FO = 32
0.5
0.5
0.6
0.7
1.0 ns
FO = 384
2.2
2.4
2.7
3.2
4.5 ns
t_SUEXT
Input Latch External FO = 32 0.0
0.0
0.0
0.0
0.0
ns
Set-Up
FO = 384 0.0
0.0
0.0
0.0
0.0
ns
t_HEXT
Input Latch External FO = 32 3.9
4.3
4.9
5.7
8.0
ns
Hold
FO = 384 4.5
4.9
5.6
6.6
9.2
ns
t_P
Minimum Period FO = 32 7.0
7.8
8.4
9.7
16.2
ns
FO = 384 7.7
8.6
9.3
10.7
17.8
ns
f_MAX
Maximum Frequency FO = 32
142
129
119
103
FO = 384
129
117
108
94
62 MHz
56 MHz
Notes:
1. For dual-module macros use tPD1 + tRD1 + taped, to + tRD1 + taped, or tPD1 + tRD1 + tusk, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1-60
v6.0