A42MX16-1PQ100ES Datasheet, PDF (15/123 Pages) Actel Corporation – 40MX and 42MX FPGA Families

40MX and 42MX FPGA Families
C_EQM =
C_EQI =
C_EQO =
C_EQCR =
Equivalent capacitance of logic modules in pF
Equivalent capacitance of input buffers in pF
Equivalent capacitance of output buffers in pF
Equivalent capacitance of routed array clock in
pF
C_L = Output load capacitance in pF
f_m = Average logic module switching rate in MHz
f_n = Average input buffer switching rate in MHz
f_p = Average output buffer switching rate in MHz
f_q1 = Average first routed array clock rate in MHz
f_q2 = Average second routed array clock rate in MHz
Fixed Capacitance Values for MX FPGAs (pF)
Device Type
r₁
routed_Clk1
r₂
routed_Clk2
A40MX02
41.4
N/A
A40MX04
68.6
N/A
A42MX09
118
118
A42MX16
165
165
A42MX24
185
185
A42MX36
220
220
Test Circuitry and Silicon Explorer II Probe
MX devices contain probing circuitry that provides built-
in access to every node in a design, via the use of Silicon
Explorer II. Silicon Explorer II is an integrated hardware
and software solution that, in conjunction with the
Designer software, allow users to examine any of the
internal nets of the device while it is operating in a
prototyping or a production system. The user can probe
into an MX device without changing the placement and
routing of the design and without using any additional
resources. Silicon Explorer II's noninvasive method does
not alter timing or loading effects, thus shortening the
debug cycle and providing a true representation of the
device under actual functional situations.
Silicon Explorer II samples data at 100 MHz
(asynchronous) or 66 MHz (synchronous). Silicon Explorer
II attaches to a PC's standard COM port, turning the PC
into a fully functional 18-channel logic analyzer. Silicon
Explorer II allows designers to complete the design
verification process at their desks and reduces
verification time from several hours per cycle to a few
seconds.
Silicon Explorer II is used to control the MODE, DCLK, SDI
and SDO pins in MX devices to select the desired nets for
debugging. The user simply assigns the selected internal
nets in the Silicon Explorer II software to the PRA/PRB
output pins for observation. Probing functionality is
activated when the MODE pin is held HIGH.
Figure 1-12 illustrates the interconnection between
Silicon Explorer II and 40MX devices, while Figure 1-13
on page 1-10 illustrates the interconnection between
Silicon Explorer II and 42MX devices
To allow for probing capabilities, the security fuses must
not be programmed. (Refer to <zBlue>“User Security”
section on page 6 for the security fuses of 40MX and
42MX devices). Table 2 on page 1-10 summarizes the
possible device configurations for probing.
PRA and PRB pins are dual-purpose pins. When the
"Reserve Probe Pin" is checked in the
Designer software, PRA and PRB pins are reserved as
dedicated outputs for probing. If PRA and PRB pins are
required as user I/Os to achieve successful layout and
"Reserve Probe Pin" is checked, the layout tool will
override the option and place user I/Os on PRA and PRB
pins.
16 Logic Analyzer Channels
Serial Connection
to Windows PC
Silicon
Explorer II
MODE
SDI
DCLK
SDO
Figure 1-12 • Silicon Explorer II Setup with 40MX
PRA
PRB
40MX
v6.0
1-9