A14100A-1CQ256B Datasheet, PDF (48/98 Pages) Actel Corporation – HiRel FPGAs

A32100DX Timing Characteristics
(Worst-Case Military Conditions, V_CC = 4.5V, T_J = 125°C)
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Logic Module Combinatorial Functions
t_PD
Internal Array Module Delay
t_PDD
Internal Decode Module Delay
Logic Module Predicted Routing Delays¹
3.1
4.1
ns
3.3
4.3
ns
t_RD1
t_RD2
t_RD3
t_RD4
t_RD5
t_RDD
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
Decode-to-Output Routing Delay
1.3
1.8
ns
1.9
2.6
ns
2.6
3.4
ns
3.3
4.3
ns
0.6
0.8
ns
0.5
0.6
ns
Logic Module Sequential Timing
t_CO
t_GO
t_SU
t_H
t_RO
t_SUENA
t_HENA
t_WCLKA
Flip-Flop Clock-to-Output
Latch Gate-to-Output
Flip-Flop (Latch) Setup Time
Flip-Flop (Latch) Hold Time
Flip-Flop (Latch) Reset to Output
Flip-Flop (Latch) Enable Setup
Flip-Flop (Latch) Enable Hold
Flip-Flop (Latch) Clock Active Pulse
Width
3.1
4.1
ns
3.1
4.1
ns
0.5
0.6
ns
0.0
0.0
ns
3.1
4.1
ns
0.9
1.2
ns
0.0
0.0
ns
4.3
5.8
ns
t_WASYN
Flip-Flop (Latch) Asynchronous Pulse
Width
5.6
7.5
ns
Note:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
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