A14100A-1CQ256B Datasheet, PDF (19/98 Pages) Actel Corporation – HiRel FPGAs

Sequential Timing Characteristics
Flip-Flops and Latches (ACT 3)
D
Y
E
CLK
CLR
(Positive edge triggered)
HiRel FPGAs
D¹
G, CLK
E
Q
CLR
t_SUD
t_HD
t_WCLKA
t_SUENA
t_HENA
t_CO
Note:
1. D represents all data functions involving A, B, and S for multiplexed flip-flops.
t_A
t_CLR
t_WASYN
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