A14100A-1CQ256B Datasheet, PDF (27/98 Pages) Actel Corporation – HiRel FPGAs

HiRel FPGAs
A1240A Timing Characteristics
(Worst-Case Military Conditions, V_CC = 4.5V, T_J = 125°C)
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Logic Module Propagation Delays¹
t_PD1
Single Module
t_CO
Sequential Clk to Q
t_GO
Latch G to Q
t_RS
Flip-Flop (Latch) Reset to Q
Logic Module Predicted Routing Delays²
5.2
6.1
ns
5.2
6.1
ns
5.2
6.1
ns
5.2
6.1
ns
t_RD1
FO=1 Routing Delay
t_RD2
FO=2 Routing Delay
t_RD3
FO=3 Routing Delay
t_RD4
FO=4 Routing Delay
t_RD8
FO=8 Routing Delay
Logic Module Sequential Timing^{3, 4}
1.9
2.2
ns
2.4
2.8
ns
3.1
3.7
ns
4.3
5.0
ns
6.6
7.7
ns
t_SUD
t_HD
t_SUENA
t_HENA
t_WCLKA
Flip-Flop (Latch) Data Input Setup
0.5
Flip-Flop (Latch) Data Input Hold
0.0
Flip-Flop (Latch) Enable Setup
1.3
Flip-Flop (Latch) Enable Hold
0.0
Flip-Flop (Latch) Clock Active Pulse
Width
7.4
0.5
ns
0.0
ns
1.3
ns
0.0
ns
8.1
ns
t_WASYN
Flip-Flop (Latch) Asynchronous Pulse
Width
7.4
8.1
ns
t_A
Flip-Flop Clock Input Period
14.8
18.6
ns
t_INH
Input Buffer Latch Hold
2.5
2.5
ns
t_INSU
Input Buffer Latch Setup
–3.5
–3.5
ns
t_OUTH
Output Buffer Latch Hold
0.0
0.0
ns
t_OUTSU
Output Buffer Latch Setup
0.5
0.5
ns
f_MAX
Flip-Flop (Latch) Clock Frequency
63
54
MHz
Notes:
1. For dual-module macros, use t_PD1 + t_RD1 + t_PDn , t_CO + t_RD1 + t_PDn , or t_PD1 + t_RD1 + t_SUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based
on actual routing delay measurements performed on the device prior to shipment.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from
the DirectTime Analyzer utility.
4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold
timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input
subtracts (adds) to the internal setup (hold) time.
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