APA075-TQ144I Datasheet, PDF (44/174 Pages) Actel Corporation – Ultra-Fast Local and Long-Line Network

ProASIC^PLUS Flash Family FPGAs
Table 1-23 • DC Specifications (3.3 V PCI Operation)¹
Commercial/
Industrial^2,3
Military/MIL-STD- 883^2,3
Symbol Parameter
Condition
Min. Max.
Min.
Max.
Units
V_DD
V_DDP
V_IH
V_IL
I_IPU
I_IL
Supply Voltage for Core
Supply Voltage for I/O Ring
Input High Voltage
Input Low Voltage
Input Pull-up Voltage⁴
Input Leakage Current⁵
2.3
2.7
2.3
2.7
V
3.0
3.6
3.0
3.6
V
0.5V_DDP V_DDP + 0.5 0.5V_DDP
V_DDP + 0.5
V
–0.5 0.3V_DDP
–0.5
0.3V_DDP
V
0.7V_DDP
0.7V_DDP
V
0 < V_IN < V_DDP Std. –10
10
–50
–F^{3, 6} –10
100
50
µA
µA
V_OH
Output High Voltage
I_OUT = –500 µA
0.9V_DDP
0.9V_DDP
V
V_OL
Output Low Voltage
I_OUT = 1500 µA
0.1V_DDP
0.1V_DDP
V
C_IN
Input Pin Capacitance (except CLK)
10
10
pF
C_CLK
CLK Pin Capacitance
5
12
5
12
pF
Notes:
1. For PCI operation, use OTB33PH, OB33PH, IOB33PH, IB33, or IB33S macro library cell only.
2. All process conditions. Junction Temperature: –40 to +110°C for Commercial and Industrial devices and –55 to +125°C for Military.
3. All –F parts are available as commercial only.
4. This specification is guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a floated
network. Designers with applications sensitive to static power utilization should ensure that the input buffer is conducting minimum
current at this input voltage.
5. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs.
6. The sum of the leakage currents for all inputs shall not exceed 2mA per device.
1-40
v5.2