APA075-TQ144I Datasheet, PDF (169/174 Pages) Actel Corporation – Ultra-Fast Local and Long-Line Network

ProASIC^PLUS Flash Family FPGAs
Previous version Changes in current version (v5.2)
Page
v3.3
The "144-Pin TQFP" table on page 2-4 was updated. The following pins changed:
page 2-4
Pin 15 = GLMX1
Pin 16 = GL1
Pin 21 = GL2
Pin 88 = GL3
Pin93 = GL4
Pin 94 = GLMX2
v3.2
The "ProASICPLUS Clock Management System" section was updated.
page 1-13
Figure 1-14 was updated.
page 1-14
Table 1-7 is new.
page 1-15
Figure 1-20 was updated.
page 1-19
The "PLL Electrical Specifications" section was updated.
page 1-21
Figure 1-26 was updated.
page 1-42
In the "Calculating Typical Power Dissipation" section, P9 was changed to 7.5 mW.
page 1-30
The "Programming, Storage, and Operating Limits" section was updated.
page 1-33
The "Recommended Design Practice for VPN/VPP" section was updated.
page 1-74
v3.1
The datasheet was updated to include references to guidelines concerning the use of certain
ProASIC^PLUS I/O standards.
v3.0
In Table 1-2 on page 1-8, the Memory Rows – Bottom coordinates were changed.
page 1-8
Figure 1-8 was updated.
page 1-8
The V_IL Minimum in the Table 1-22 was changed from 0.3 to –0.3.
page 1-38
In the "Output Buffer Delays" section, the OB25LPLL t_DHL Standard changed to 5.3.
page 1-44
In the "Sample Macrocell Library Listing" section, the AND2 Standard maximum changed to 0.7 page 1-51
and the –F maximum changed to 0.8.
v2.0
The Table 1 was updated.
page i-i
The "Ordering Information" section was updated.
page i-ii
The "Plastic Device Resources" section was updated.
page i-ii
The "ProASICPLUS Architecture" section was updated.
page 1-2
Table 1-2 was updated.
page 1-8
Table 1-8 is new.
page 1-16
Figure 1-11 is new.
page 1-10
The Introduction section in the "ProASICPLUS Clock Management System" section was page 1-13
updated.
The "Physical Implementation" section was updated.
page 1-13
The "Functional Description" on page 1-13 was updated.
page 1-13
Figure 1-14 on page 1-14 through Figure 1-20 on page 1-19 were updated.
page 1-14 to page
1-19
The "PLL Electrical Specifications" on page 1-21 was updated.
page 1-21
Figure 1-25 on page 1-26 was updated.
page 1-26
The "Calculating Typical Power Dissipation" on page 1-30 was updated.
page 1-30
The ’Nominal Supply Voltages’ section was updated.
page 1-34
The Table 1-22 was updated.
page 1-38
The "Tristate Buffer Delays" on page 1-42 was updated.
page 1-42
The "Output Buffer Delays" on page 1-44 was updated.
page 1-44
The"Input Buffer Delays" on page 1-46 was updated.
page 1-46
"Global Routing Skew" on page 1-50 was updated.
page 1-50
The"Sample Macrocell Library Listing" on page 1-51 was updated.
page 1-51
v5.2
3-3