COREU1LL-XX Datasheet, PDF (4/8 Pages) Actel Corporation – CoreU1LL UTOPIA Level 1 Link-Layer Interface

CoreU1LL UTOPIA Level 1 Link-Layer Interface
"write" interface. Conversely, the CoreU1LL accepts a
standard 54-byte cell at the user "read" interface and
drops the sixth byte during the transfer to the egress (Tx)
interface. If xlate is high, no translation is performed; 54-
byte cells are transferred on all interfaces.
The user interface is divided into write (Rx) and read (Tx)
interfaces. The control signals and data for the write
interface are associated with the u1_rx_clk, while control
signals and data for the read interface are associated
with the u1_tx_clk.
Each interface is controlled from the user logic by the
w_avail and r_avail signals, respectively.
When the cell buffer or user logic is ready to receive or
send a cell on either interface, the user must assert
x_avail high. In turn, this causes the CoreU1LL to assert
u1_x_en to the PHY-Layer device provided that u1_x_clav
is asserted (high).
(u1_rx_clav is high) and user logic is able to accept
another cell (w_avail remains high), the w_phy_act signal
remains active (high), and the CoreU1LL block accepts a
back-to-back cell from the PHY-Layer device. The
CoreU1LL will wait for the PHY-Layer to assert u1_rx_soc
and then begins asserting w_enable during each valid
data word and incrementing w_adr (Figure 8).
Read Interface (Egress)
When r_avail is asserted high at the user interface and
the u1_tx_en signal is asserted low by the CoreU1LL, the
CoreU1LL begins accepting data on the user interface.
Once a cell transfer has begun, the CoreU1LL transfers 27
words of data regardless of the state of r_avail. The
CoreU1LL asserts r_buf_en high, expecting to accept data
at the r_data inputs on the next rising-edge of u1_tx_clk,
as illustrated in Figure 9 on page 4.
Write Interface
Whenever the CoreU1LL asserts u1_rx_en low, the
w_phy_act signal is asserted high to indicate that the
ingress user interface is active. The w_enable signal will
remain low until the link-layer begins to transfer a cell.
Since the CoreU1LL translates from 8-bit data at the
UTOPIA interface to 16-bit data at the user interface,
w_enable is asserted for one clock cycle while a data
word is valid. W_adr is incremented on the next rising-
edge of u1_rx_clk, and then w_enable is deasserted for
one clock cycle (except during insertion of the UDF2
byte, as shown in Figure 8). W_adr increments from 00 to
1B hex (27 words).
u1_rx_clk
u1_rx_clav
u1_rx_en
u1_rx_soc
u1_rx_data
w_phy_act
w_enable
w_adr
w_data
XX H1 H2 H3 H4 H5 P1 P2 P3
00
01 02 03
XX
H1H2 XX H3H4 H5H5 XX P1P2
Figure 8 • Write Interface Cell Transfer
Once a complete 54-byte cell has been written to the
user interface (w_adr = 1B hex and w_enable high),
w_adr will reset to 00 hex, and w_enable will be
deasserted. If either u1_rx_clav or w_avail are deasserted
(low), then the CoreU1LL deselects the PHY-Layer device
and w_phy_act returns low (inactive). On the other hand,
if the PHY-Layer device is prepared to send another cell
u1_tx_cl
u1_tx_cla
u1_tx_en
u1_tx_soc
u1_tx_data
r_buf_en
r_adr
XX
H1 H2 H3 H4 H5 P1 P2
00
01
02
03
04
r_data XX
H1H2 H3H4 H5H6 P1P2
Figure 9 • Read Interface Cell Transfer
The CoreU1LL provides r_adr as a word count (00 to 1B
hex) and increments whenever the core accepts data at
the r_data pins. Since the CoreU1LL translates from 16-
bit data at the user interface to 8-bit data at the UTOPIA
interface, r_buf_en is asserted for one clock cycle. Data is
accepted on the following rising edge of u1_tx_clk, and
the r_adr is incremented.
Then r_buf_en is deasserted for one clock cycle, except
after the third data word when xlate is low (53-byte
mode), or when a back-to-back read operation is needed
in order to get the first payload byte in time.
The cycle is repeated until r_adr reaches 1B hex and the
last two bytes of the ATM cell are sent. At this point
r_adr is reset to 00 hex. If r_avail indicates that another
cell is immediately available, and u1_tx_clav remains
high, the CoreU1LL will immediately begin sending the
next cell (Figure 10 on page 5). Otherwise r_buf_en
remains low until the CoreU1LL begins to transmit
another cell.
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