COREU1LL-XX Datasheet, PDF (2/8 Pages) Actel Corporation – CoreU1LL UTOPIA Level 1 Link-Layer Interface

CoreU1LL UTOPIA Level 1 Link-Layer Interface
Device Requirements
CoreU1LL can be implemented in either ProASIC^PLUS or Axcelerator device families. Table 1 indicates the number of
core logic cells required in each technology.
Table 1 • Device Utilization and Performance
Cells or Tiles
Total Utilization
Family
Sequential Combinatorial
Device
Percentage
Performance
Fusion
51
66
AFS060
7.8%
>25 MHz
ProASIC3/E
ProASIC^PLUS
51
66
A3P060
7.8%
>25 MHz
51
79
APA075
4.2%
>25 MHz
Axcelerator
53
64
AX125
6.0%
>25 MHz
UTOPIA Interface
CoreU1LL implements a standard 8-bit point-to-point
PHY-Layer interface that supports cell lengths of either
53 or 54 bytes. If the cell_size bit is low, a 53-byte cell is
transferred and the UDF2 byte is inserted on ingress to,
and dropped on egress from, the user interface;
otherwise, 54 bytes are transferred. The UTOPIA
interface signals are summarized in Table 2.
Table 2 • UTOPIA Interface Signals
Signal
Type Description
u1_tx_clk
In Tx interface clock
u1_tx_clav
In Active high cell buffer space available
u1_tx_en
Out Active low data transfer enable
u1_tx_soc
Out Active high start-of-cell indication
u1_tx_data Out 8-bit egress data
u1_rx_clk
In Rx interface clock
u1_rx_clav
In Active high cell buffer space available
u1_rx_en
Out Active low data transfer enable
u1_rx_soc
In Active high start-of-cell indication
u1_rx_data In 8-bit ingress data
Tx Interface (Egress)
The process of transferring a cell on the UTOPIA level 1
Tx interface begins with r_avail. User logic asserts r_avail
high whenever it has a cell available to send. The
CoreU1LL waits until the PHY-Layer device indicates that
it is ready to receive a cell by asserting u1-tx_clav high.
To begin sending cells on the Tx interface, the CoreU1LL
asserts u1_tx_en low (Figure 2). CoreU1LL simultaneously
asserts u1_tx_soc and u1_tx_data (Figure 2). The core
sends 53 bytes (or 54 bytes) and does not monitor
u1_tx_clav during cell transfers.
u1_tx_clk
u1_tx_clav
u1_tx_en
u1_tx_soc
u1_tx_data
H1 H2
Figure 2 • Tx Start of Cell
If the user interface indicates that there are no more cells
to send, or if polling during the current cell transfer
indicates that the PHY-Layer device is not ready to accept
another cell, the CoreU1LL deselects the physical
interface by deasserting u1_tx_en after the last word of
the transfer (Figure 3).
u1_tx_clk
u1_tx_clav
u1_tx_en
u1_tx_soc
u1_tx_data _{P51 P52 P53 P54}
XX
Figure 3 • Tx Transfer Complete
If the user interface has another cell to send to the PHY-
Layer device, and if polling during the current cell
indicates that the PHY-Layer device can accept another
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