COREU1LL-XX Datasheet, PDF (1/8 Pages) Actel Corporation – CoreU1LL UTOPIA Level 1 Link-Layer Interface

CoreU1LL UTOPIA Level 1 Link-Layer Interface
Product Summary
Intended Use
• Standard UTOPIA Level 1 Interface to any ATM
PHY-Layer Device
Key Features
• Standard 8-Bit, 25 MHz UTOPIA Level 1 Link-Layer
(Master) Interface Complies with the ATM Forum
UTOPIA Specification, Level 1 Version 2.01 (af-phy-
0017.000)
• Separate Tx and Rx Clocks and Interface Pins
• Supports Cell-Level Handshake for 53- or 54-byte
ATM Cells with Automatic Add/Drop of the UDF2
Field in the ATM Header in 53-byte Mode
• 16-Bit (54-byte) User Interfaces can be Used
Directly or Bolt-Up to One of Actel's ATM Cell
Buffer Blocks: ATMBUFx
Supported Families
• Fusion
• ProASIC3/E
• ProASIC^PLUS®
• Axcelerator^®
IDE and Industry Standard Synthesis and
Simulation Tools
• RTL Version
– VHDL Source Code
– Core Synthesis and Simulation Scripts
• Actel-Developed Testbench (VHDL) Fully
Supported by Industry-Standard Simulation Tools
Design Tools Support
• Simulation: VITAL-Compliant VHDL and OVI-
Compliant Verilog Simulators
• Synthesis: LeonardoSpectrum^TM, Synplify^®, Design
Compiler^®, FPGA Compiler^TM, and FPGA Express^TM
Contents
General Description ................................................... 1
Device Requirements ................................................. 2
UTOPIA Interface ....................................................... 2
User Interface ............................................................. 3
Ordering Information ................................................ 6
List of Changes ........................................................... 7
Datasheet Categories ................................................. 7
Core Deliverables
• Netlist Version
– Compiled RTL Simulation Model Fully
Supported in the Actel Libero^® Integrated
Design Environment (IDE)
– Structural VHDL and Verilog Netlists (with and
without I/O Pads) Compatible with Actel Libero
General Description
CoreU1LL is a UTOPIA Level 1 Link-Layer (Master)
interface core that connects directly to any ATM PHY-
Layer (Slave) device and user logic (or optional ATM cell
buffer blocks) to provide an interface between the PHY-
Layer device and a non-standard Link-Layer device or
user logic (Figure 1).
RX
Utopia
Level 1
PHY-Layer _TX
Device
Figure 1 • Block Diagram
CoreU1LL
CoreATMBUF3
CoreATMBUF3
User
Logic
Other
Device
December 2005
v4.0
1
© 2005 Actel Corporation