A1020B-PL44C Datasheet, PDF (31/98 Pages) Actel Corporation – Highly Predictable Performance with Automatic Placement and Routing

HiRel FPGAs
A1280A Timing Characteristics (continued)
(Worst-Case Military Conditions, V_CC = 4.5V, T_J = 125°C)
‘–1’ Speed
‘Std’ Speed
Parameter Description
Min.
Max.
Min.
Max.
Units
Input Module Propagation Delays
t_INYH
Pad to Y High
t_INYL
Pad to Y Low
t_INGH
G to Y High
t_INGL
G to Y Low
Input Module Predicted Routing Delays¹
t_RD1
FO=1 Routing Delay
t_RD2
FO=2 Routing Delay
t_RD3
FO=3 Routing Delay
t_RD4
FO=4 Routing Delay
t_RD8
FO=8 Routing Delay
Global Clock Network
4.0
4.7
ns
3.6
4.3
ns
6.9
8.1
ns
6.6
7.7
ns
6.2
7.3
ns
7.2
8.4
ns
7.7
9.1
ns
8.9
10.5
ns
12.9
15.2
ns
t_CKH
Input Low to High
FO = 32
FO = 384
13.3
17.9
15.7
21.1
ns
t_CKL
Input High to Low
FO = 32
FO = 384
13.3
18.2
15.7
21.4
ns
t_PWH
Minimum Pulse Width High
FO = 32
6.9
FO = 384
7.9
8.1
9.3
ns
t_PWL
Minimum Pulse Width Low
FO = 32
6.9
FO = 384
7.9
8.1
9.3
ns
t_CKSW
Maximum Skew
FO = 32
0.6
FO = 384
3.1
0.6
3.1
ns
t_SUEXT
Input Latch External Setup
FO = 32
0.0
FO = 384
0.0
0.0
0.0
ns
t_HEXT
Input Latch External Hold
FO = 32
8.6
FO = 384
13.8
8.6
13.8
ns
t_P
Minimum Period
FO = 32
13.7
FO = 384
16.0
16.2
18.9
ns
f_MAX
Maximum Frequency
FO = 32
73
FO = 384
63
62
53
MHz
Note:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based
on actual routing delay measurements performed on the device prior to shipment. Optimization techniques may further reduce delays by 0
to 4 ns.
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