APA150-TQG100 Datasheet, PDF (29/178 Pages) Actel Corporation – ProASICPLUS® Flash Family FPGAs

ProASIC^PLUS Flash Family FPGAs
PLL I/O Constraints
PLL locking is guaranteed only when the following constraints are followed:
Table 2-10 • PLL I/O Constraints
T_J ≤ –40°C
Value T_J > –40°C
I/O Type
PLL locking is guaranteed only when using low drive strength and
low slew rate I/O. PLL locking may be inconsistent when using high
drive strength or high slew rate I/Os
No Constraints
SSO
APA300
Hermetic packages ≤ 8 SSO
With FIN ≤ 180 MHz and
Plastic packages ≤ 16 SSO
outputs
simultaneously
switching
APA600
Hermetic packages ≤ 16 SSO
APA1000
APA300
APA600
APA1000
Plastic packages ≤ 32 SSO
Hermetic packages ≤ 16 SSO
Plastic packages ≤ 32 SSO
Hermetic packages ≤ 12 SSO
Plastic packages ≤ 20 SSO
Hermetic packages ≤ 32 SSO
Plastic packages ≤ 64 SSO
Hermetic packages ≤ 32 SSO
Plastic packages ≤ 64 SSO
With FIN ≤ 50 MHz and half
outputs switching on positive
clock edge, half switching on
the negative clock edge no less
than 10 ns later
v5.9
2-19