1553BRT-EBR Datasheet, PDF (18/28 Pages) Actel Corporation – Core1553BRT-EBR Enhanced Bit Rate 1553 Remote Terminal

Core1553BRT-EBR Enhanced Bit Rate 1553 Remote Terminal
Command Legalization Interface
1553EBR commands can be legalized in two ways with the Core1553BRT-EBR. For RTL versions, one of the modules in
the source code can be edited to legalize or make illegal command words based on the sub-address, mode code, word
count, or broadcast fields of the command word. For netlist and RTL versions, external logic may be used to decode the
legal/illegal command words (see Figure 8).
The user customization logic block takes in the CMDVAL and simply sets CMDOKAY for all legal command words. The
CMDVAL encoding is given in Table 13. The external logic must implement this function within 3 µs.
Core1553BRT-EBR
USEEXTOK
CMDVAL[11:0]
CMDOKAY
'1'
User
Customization
Logic
Actel FPGA
Figure 8 • Command Legalization Logic
Table 13 • CMDVAL Encoding
Bit(s)
Function
Description
11 Broadcast
'1' indicates broadcast, i.e., the RT address was set to 31 in the 1553EBR command word.
10 Transmit or Receive TX/RX field from the 1553EBR command word. '0' indicates receive and '1' transmit.
9:5 Sub-Address
Sub-address field from the 1553EBR command word
4:0 Word Count
Mode Code
Word count field from the 1553EBR command word. When the sub-address is 0 or 31, this contains the
1553EBR mode code.
Bus Transceivers
Core1553BRT-EBR drives the 1553EBR bus through
standard RS485 transceivers, such as the Texas Instruments
SN65HVD10. Typical connections are shown in Figure 9 on
page 19.
It is recommended that the transceiver used support 3.3 V
operation to allow direct connection to the 3.3 V I/Os on
the FPGA.
Typical RT Systems
The Core1553BRT-EBR can be used in systems with and
without backend memory. Figure 9 on page 19 shows a
typical implementation for a system with backend
memory and a CPU to process the messages. Figure 10 on
page 19 shows a system with direct connection between
the Core1553BRT-EBR and external analog-to-digital
converters, etc. In this case, any glue logic required
between the core and the device being interfaced to can
simply be implemented within the FPGA containing the
core.
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