1553BRT-EBR Datasheet, PDF (1/28 Pages) Actel Corporation – Core1553BRT-EBR Enhanced Bit Rate 1553 Remote Terminal

Core1553BRT-EBR Enhanced Bit Rate 1553
Remote Terminal
Advanced v1.1
Product Summary
Intended Use
• 1553 Enhanced Bit Rate Remote Terminal (RT)
• DMA Backend Interface to External Memory
• Direct Backend Interface to Devices
• Space and Avionic Applications
Key Features
• Supports Enhanced Bit Rate 1553
• 10 Mbps Time-Multiplexed Serial Data Bus
• Interfaces to External RAM or Directly to Backend
Device
• Synchronous or Asynchronous Backend Interface
• Encoders and Decoders Operate off 100 MHz Clock
• Protocol Control and Memory Interface Operates
off 50 MHz Clock
• Interfaces to Standard RS485 Transceivers
• Programmable Mode Code and Sub-Address
Legality for Illegal Command Support
• Memory Address Mapping Allowing Emulation of
Legacy Remote Terminals
• Fail-Safe State Machines
• Fully Synchronous Operation
Supported Families
• ProASIC^®3/E
• ProASIC^PLUS®
• Axcelerator^®
• RTAX-S
Core Deliverables
• Netlist Version
– Compiled RTL Simulation Model, Compliant with
Actel Libero^® Integrated Design Environment (IDE)
– Netlist Compatible with the Actel Designer
Place-and-Route Tool (with and without I/O Pads)
• RTL Version
– VHDL or Verilog Core Source Code
– Synthesis Scripts
• Actel-Developed Testbench (VHDL)
Development System
• Complete 1553BRT-EBR Implementation, Implemented
in an AX1000
Synthesis and Simulation Support
• Synthesis: Exemplar™, Synplicity^®, Design Compiler^®,
FPGA Compiler™
• Simulation: Vital-Compliant VHDL Simulators and
OVI-Compliant Verilog Simulators
Verification and Compliance
• Meets Requirements of Draft SAE AS5682 Standard
(2005-10)
• Actel-Developed Simulation Testbench Implements
a Subset of the RT Test Plan (MIL-HDBK-1553A) for
Protocol Verification
• Protocol Control Derived from Core1553BRT,
which Is Certified to MIL-STD-1553B (RT Validation
Test Plan MIL-HDBK-1553, Appendix A)
Contents
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Core1553BRT-EBR Device Requirements . . . . . . . . . . . . 4
Core1553BRT-EBR Verification and Compliance . . . . . . 4
Core1553BRT-EBR Fail-Safe State Machines . . . . . . . . . . 4
Enhanced Bit Rate 1553 Bus Overview . . . . . . . . . . . . . . 4
I/O Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1553BRT-EBR Operation . . . . . . . . . . . . . . . . . . . . . . . . 14
Command Legalization Interface . . . . . . . . . . . . . . . . . 18
Bus Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Typical RT Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Transceiver Loopback Delays . . . . . . . . . . . . . . . . . . . . 25
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . 25
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . 26
February 2006
Advanced v1.1
1
© 2006 Actel Corporation