1553BRT-EBR Datasheet, PDF (14/28 Pages) Actel Corporation – Core1553BRT-EBR Enhanced Bit Rate 1553 Remote Terminal

Core1553BRT-EBR Enhanced Bit Rate 1553 Remote Terminal
Table 9 • Transfer Status Word
Bit(s) Name
Description
15
USED
This bit is set to '1' at the end of the transmit or receive command.
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OKAY Indicates that no errors are detected, i.e., bits 11 to 5 are all '0'
13
BUSN Indicates on which bus the command was received
'0': BUSA '1': BUSB
12
BROADCAST Indicates a broadcast command
11
LPBKERRB Indicates that the loopback logic detected an error on the transmitted data for bus B
10
LPBKERRA Indicates that the loopback logic detected an error on the transmitted data for bus A
9
ILLEGAL CMD The command was illegal. Either a request to transmit from an illegal sub-address or an illegal mode code was
received.
8
MEMIFERR Indicates that the DMA memory access failed to complete quickly enough
7
MANERR Indicates that a Manchester encoding error was detected in the incoming data
6
PARERR Indicates that a parity error was detected in the incoming data
5
WCNTERR Indicates that an incorrect number of words was received
4:0
COUNT SA1 to SA31 Indicates the number of words received or transmitted for that sub-address. If WCNTERR is
'0', '00000' indicates 32 words. Otherwise, '00000' indicates zero words transferred.
SA0 or SA31 Indicates which mode code was received or transmitted per the 1553EBR specification
1553BRT-EBR Operation
Data Transfers – Receive
When a receive data transfer command is detected, the
core will decode each incoming word. At the end of each
word, the core will assert MEMREQn. When MEMGNTn
goes low, it will write the data word to the memory and
release the MEMREQn. This process is repeated until the
correct number of words has been transferred. The core
will then transmit its 1553EBR status word. Finally, the
TSW is also written to memory.
Data Transfers – Transmit
When a transmit data transfer command is detected, the
core will transmit its status word and assert MEMREQn.
When MEMGNTn goes low, it will read a data word from
the memory and release the MEMREQn. Once the word
is available, the core will transmit the data word. The
core will continue to request data from the memory
interface until the required number of words has been
transferred. Finally, the TSW is written to memory.
RT-to-RT Transfer Support
The 1553EBR specification (SAE AS5682) does not
support RT-to-RT transfers. Likewise, Core1553BRT-EBR
does not support RT-to-RT transfers.
Mode Codes
When the core receives a mode code, it first checks its
command validity. If the command is valid, it is processed
in accordance with the specification. Otherwise, the
message error bit will be set in the 1553EBR status word.
Table 10 on page 15 lists the supported mode codes.
Two mode codes, (1) transmit a vector word and (2)
synchronize with data, require external data. When
EXTMDATA is inactive, the vector word value is set by the
VWORD input and the synchronize with data word is
discarded. When EXTMDATA is active, these values are
read from and written to memory. The MEMADDR
output will be similar to a single-word data transfer
message. Bit 10 will reflect the command word TX bit,
and bits 9:5 will be 00h or 1Fh, depending on whether
the mode code sub-address is set to 0 or 31. Bits 4:0 will
be zero. This implies that the vector word will be read
from location 400h or 7E0h, and the synchronize with
data word is written to location 000h or 3E0h,
depending on whether sub-address 0 or 31 is used.
When both WRTCMD and WRTTSW are active for each
message, the command word and TSW value will be
written to the same location. These writes can be
distinguished by the MEMOPER output. This may cause
some system problems, but such can be avoided by
implementing an external address mapper function to
map these accesses to different addresses.
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