ACE25C100G Datasheet, PDF (5/37 Pages) ACE Technology Co., LTD. – Uniform Sector Dual and Quad Serial Flash

ACE25C100G
Uniform Sector Dual and Quad Serial Flash
Hold
The HOLD# signal goes low to stop any serial communications with the device, but doesn’t stop the
operation of write status register, programming, or erasing in progress.
The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with
SCLK signal being low (if SCLK is not being low, HOLD operation will not start until SCLK being low).
The HOLD condition ends on rising edge of HOLD# signal with SCLK being low (If SCLK is not being
low, HOLD operation will not end until SCLK being low).
The SO is high impedance, both SI and SCLK don’t care during the HOLD operation, if CS# drives
high during HOLD operation, it will reset the internal logic of the device. To re-start communication
with chip, the HOLD# must be at high and then CS# must be at low.
Figure1. Hold Condition
Data Protection
The ACE25C100G provide the following data protection methods:
 Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL).
The WEL bit will return to reset by the following situation:
-Power-Up
-Write Disable (WRDI)
-Write Status Register(WRSR)
-Page Program (PP)
-Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)
 Software Protection Mode: The Block Protect (SEC, TB, BP2, BP1, BP0) bits define the section
of the memory array that can be read but not change.
 Hardware Protection Mode: WP# going low to protected the BP0~SEC bits and SRP0~1 bits.
 Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the
Release from deep Power-Down Mode command.
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