ACE25AC200G Datasheet, PDF (5/24 Pages) ACE Technology Co., LTD. – SPI NOR FLASH

ACE25AC200G
SPI NOR FLASH
WEL bit.
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1,
the internal Write Enable Latch is set. When set to 0, the internal Write Enable Latch is reset and no Write
Status Register, Program or Erase command is accepted.
BP2, BP1, BP0 bits.
The Block Protect (BP2, BP1, and BP0) bits are non-volatile. They define the size of the area to be
software protected against Program and Erase commands. These bits are written with the Write Status
Register (WRSR) command. When the Block Protect (BP2, BP1, and BP0) bits are set to 1, the relevant
memory area (as defined in Table1) becomes protected against Page Program (PP), Sector Erase (SE)
and Block Erase (BE) commands. Chip Erase command will be ignored if one or more of the Block
Protect (BP2, BP1, and BP0) bits are 1.
SRWD bit.
The Status Register Write Disable (SRWD) bit is a non-volatile One Time Program (OTP) bit in the status
register that provide another software protection. Once it is set to 1, the Write Status Register (WRSR)
instruction is no longer accepted and the SRWD bit and Block Protect bits (BP2, BP1, and BP0) are read
only.
SRWD
Status register
Memory
Status register can be written in (WEL bit is
0 set to "1") and the SRWD, BP2-BP0 bits can The protected area cannot be program or erase
be changed
The SRWD, BP2-BP0 of status register bits
1
The protected area cannot be program or erase
cannot be changed
Commands Description
All commands, addresses and data are shifted in and out of the device, beginning with the most
significant bit on the first rising edge of SCLK after CS# is driven low. Then, the one-byte command code
must be shifted in to the device, most significant bit first on SI, each bit being latched on the rising edges
of SCLK. See Table2, every command sequence starts with a one-byte command code. Depending on
the command, this might be followed by address bytes, or by data bytes, or by both or none. CS# must be
driven high after the last bit of the command sequence has been shifted in. For the command of Read,
Fast Read, Read Status Register, and Read Device ID, the shifted-in command sequence is followed by a
data-out sequence. CS# can be driven high after any bit of the data-out sequence is being shifted out.
For the command of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write
Enable, Write Disable, CS# must be driven high exactly at a byte boundary, otherwise the command is
rejected. That is CS# must driven high when the number of clock pulses after CS# being driven low is an
exact multiple of eight. For Page Program, if at any time the input byte is not a full byte, nothing will
happen and WEL will not be reset.
VER 1.2 5