ACE25AC200G Datasheet, PDF (4/24 Pages) ACE Technology Co., LTD. – SPI NOR FLASH

ACE25AC200G
SPI NOR FLASH
Data Protection
The ACE25AC200G provides the following data protection methods:
Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL
bit will return to reset by the following situation:
 Power-Up
 Write Disable (WRDI)
 Write Status Register (WRSR)
 Page Program (PP)
 Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)
Software Protection Mode:
 SRWD=0, the Block Protect (BP2, BP1, and BP0) bits define the section of the memory array that
can be read but not change
SRWD=1, the Write Status Register (WRSR) instruction is no longer accepted for execution and the
 SRWD bit and Block Protect bits (BP2, BP1, and BP0) are read only.
Table 1.ACE25AC200G Protected Area Sizes
Status bit
BP2
BP1
BP0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Protect level
0(none)
1 (1 block)
2 (2 blocks)
3 (4 blocks)
4 (8 blocks)
5 (All)
6 (All)
7 (All)
Protect Block
None
Block 7
Block 6-7
Block 4-7
All
All
All
All
Status Register
S7
S6
S5
S4
S3
S2
S1
S0
SRWD Reserved Reserved
BP2
BP1
BP0
WEL
WIP
The status and control bits of the Status Register are as follows:
WIP bit.
The Write In Progress (WIP) bit indicates whether the memory is busy in program/erase/write status
register progress. When WIP bit sets to 1, the device is busy in program/erase/write status register
progress. When WIP bit sets 0, the device is not in program, erase or write status register.
VER 1.2 4