ACE25AC200G Datasheet, PDF (3/24 Pages) ACE Technology Co., LTD. – SPI NOR FLASH

Block Diagram
ACE25AC200G
SPI NOR FLASH
Uniform Block Sector Architecture
ACE25AC200G 64K Bytes Block Sector Architecture
Block
Sector
63
3
……
48
47
2
……
32
31
1
……
16
15
0
……
0
Address Range
03F000H
03FFFFH
……
……
030000H
030FFFH
02F000H
02FFFFH
……
……
020000H
020FFFH
01F000H
01FFFFH
……
……
010000H
010FFFH
00F000H
00FFFFH
……
……
000000H
000FFFH
Device Operation
The ACE25AC200G features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip
Select (CS#), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are
supported. Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of
SCLK.
VER 1.2 3