ACE25C400G Datasheet, PDF (16/39 Pages) ACE Technology Co., LTD. – Uniform SECTOR Dual and Quad Serial Flash

ACE25C400G
Uniform SECTOR Dual and Quad Serial Flash
Quad Output Fast Read (6BH)
The Quad Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte,
each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out
4-bit per clock cycle from IO3, IO2, IO1 and IO0. The command sequence is shown in followed
Figure9. The first byte addressed can be at any location. The address is automatically incremented to
the next higher address after each byte of data is shifted out.
Figure9. Quad Output Fast Read Sequence Diagram
Dual I/O Fast Read (BBH)
The Dual I/O Fast Read command is similar to the Dual Output Fast Read command but with the
capability to input the 3-byte address (A23-0) and a “Continuous Read Mode” byte 2-bit per clock by
SI and SO, each bit being latched in during the rising edge of SCLK, then the memory contents are
shifted out 2-bit per clock cycle from SI and SO. The command sequence is shown in followed
Figure10. The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out.
VER 1.5 16