R11-0869 Datasheet, PDF (8/16 Pages) A-Data Technology – AD3V1600W8G11 DDR3-1600(CL11) 240-Pin VLP R-DIMM 8GB(1024Mx72-bits)

AD3V1600W8G11
DDR3-1600(CL11) 240-Pin VLP R-DIMM
8GB(1024Mx72-bits)
SCL
SA0~SA2
ODT0~ODT1
PAR_IN
/RESET
/ERR_OUT
/EVENT
NC
Serial clock
EEPROM clock input
Address in EEPROM EEPROM address input
On Die Termination
When high, termination resistance is enabled for all DQ, /DQ and DM pins, assuming the
function is enabled in the Extended Mode Register Set.
Parity input
Parity bit for the command and address bus. ("1 " : Odd, "0 ": Even)
Reset
/RESET is an active LOW CMOS input referenced to VSS. The RESET# input receiver is a
CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × VDD and DC LOW ≤ 0.2 ×
VDD. RESET# assertion and deassertion are asynchronous.
Parity error output: Parity error found on the command and address bus.
Thermal EVENT
This signal indicates that a thermal event has been detected in the thermal sensing
device.The system should guarantee the electrical level requirement is met for the EVENT pin
on TS/SPD part.
No Connection
This pin is recommended to be left No Connection on the device.
8