IC41C16100S Datasheet, PDF (4/21 Pages) Integrated Circuit Solution Inc – 1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE

IC41C16100S
IC41LV16100S
TRUTH TABLE
Function
Standby
Read: Word
Read: Lower Byte
RAS
H
L
L
LCAS UCAS WE
H
H
X
L
L
H
L
H
H
OE Address tR/tC
X
X
L
ROW/COL
L
ROW/COL
Read: Upper Byte
L
H
L
H
L
ROW/COL
Write: Word (Early Write)
Write: Lower Byte (Early Write)
L
L
L
L
X
ROW/COL
L
L
H
L
X
ROW/COL
Write: Upper Byte (Early Write)
L
H
L
L
X
ROW/COL
Read-Write^(1,2)
EDO Page-Mode Read⁽²⁾
EDO Page-Mode Write⁽¹⁾
EDO Page-Mode^(1,2)
Read-Write
Hidden Refresh
RAS-Only Refresh
CBR Refresh⁽⁴⁾
L
1st Cycle: L
2nd Cycle: L
Any Cycle: L
1st Cycle: L
2nd Cycle: L
1st Cycle: L
2nd Cycle: L
Read⁽²⁾ L→H→L
Write^(1,3) L→H→L
L
H→L
L
H→L
H→L
L→H
H→L
H→L
H→L
H→L
L
L
H
L
L
H→L
H→L
L→H
H→L
H→L
H→L
H→L
L
L
H
L
H→L
H
H
H
L
L
H→L
H→L
H
L
X
X
L→H
L
L
L
X
X
L→H
L→H
L
X
X
X
ROW/COL
ROW/COL
NA/COL
NA/NA
ROW/COL
NA/COL
ROW/COL
NA/COL
ROW/COL
ROW/COL
ROW/NA
X
Notes:
1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).
2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).
3. EARLY WRITE only.
4. At least one of the two CAS signals must be active (LCAS or UCAS).
I/O
High-Z
DOUT
Lower Byte, DOUT
Upper Byte, High-Z
Lower Byte, High-Z
Upper Byte, DOUT
DIN
Lower Byte, DIN
Upper Byte, High-Z
Lower Byte, High-Z
Upper Byte, DIN
DOUT, DIN
DOUT
DOUT
DOUT
DIN
DIN
DOUT, DIN
DOUT, DIN
DOUT
DOUT
High-Z
High-Z
4
Integrated Circuit Solution Inc.
DR010-0D 11/26/2004