M1T1HT18PZ32E Datasheet, PDF (5/6 Pages) List of Unclassifed Manufacturers – High Speed Pipelined 1-Mbit (32Kx32) Standard 1T-SRAM Embedded Memory Macro

OPERATION TRUTH TABLE
High Speed Pipelined 1-Mbit (32Kx32)
Standard 1T-SRAM^® Embedded Memory Macro
M1T1HT18PZ32E
rdb
wrb
0
0
0
1
1
0
1
1
Operation
Illegal
Read
Write
Nop
FUNCTIONAL OPERATION
Address and command clocked in by rising clock edge. Read data transfers occur in the clock cycle following
the next clock rising edge. Write data transfers occur in the following clock cycle This standard macro uses
user-managed refresh hiding. Review conditions with MoSys to finalize the specification.
clk
adr
A
rdb
dout
rD
S
Single Cycle Read Timing
clk
adr
bweb
A
wrb
din
rW
Single Cycle Write
M1T1HT18PZ32E Rev 2.doc
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