M1T1HT18PZ32E Datasheet, PDF (4/6 Pages) List of Unclassifed Manufacturers – High Speed Pipelined 1-Mbit (32Kx32) Standard 1T-SRAM Embedded Memory Macro

High Speed Pipelined 1-Mbit (32Kx32)
Standard 1T-SRAM^® Embedded Memory Macro
M1T1HT18PZ32E
Memory macro implements a synchronous reset to force state machines into a known state after power-up.
This reset does not clear the memory contents. The clock must be running for at least two cycles before the
Reset (rstb) signal will be correctly sampled as shown above. The Reset (rstb) signal must be active for at
least ten (10) clock periods to initialize all internal circuitry. Independent of the Reset (rstb) signal, after power
has stabilized to a voltage within the operating specification and the clock is operating within its timing
specifications, there must be at least 128 clock cycles before any read or write access.
clk
rstb
rdb or wrb
>128 clk
>10 clk
Initialization Timing
M1T1HT18PZ32E Rev 2.doc
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