ZADCS146 Datasheet, PDF (6/19 Pages) Zentrum Mikroelektronik Dresden AG – 12-Bit, 200ksps, 8-Channel, Serial Output ADC

Datasheet
ZADCS146 / ZADCS147
1.3.2 ZADCS146 Specific Parameters
(VDD = +2.7V to + 5.25V; fSCLK = 3.2MHz (50% duty cycle); 16 clocks/conversion cycle (200 ksps); qOP = qOPmin … qOPmax)
Parameter
Symbol Conditions
Min Typ Max Unit
Internal Reference at VREF
VREF Output Voltage
TA = + 25°C
2.480
VREF Short-Circuit Current
VREF Temperature Coefficient
Load Regulation
0 to 0.2mA output load
Capacitive Bypass at VREF
4.7
Capacitive Bypass at REFADJ
0.047
REFADJ Adjustment Range
External Reference at VREF (internal buffer disabled by V(REFADJ) = VDD)
VREF Input Voltage Range
1.0
VREF Input Current
VREF = 2.5V
VREF Input Resistance
11.5
Shutdown VREF Input Current
2.500
± 30
0.35
± 1.5
2.520
30
± 50
V
mA
ppm/°C
mV
µF
µF
%
VDD +
50mV
V
180 215 µA
14
kW
0.1 µA
REFADJ Buffer Disable Threshold
VDD-
0.5
V
External Reference at VREF_ADJ
Reference Buffer Gain
VREF_ADJ Input Current
Full Power Down
VREFADJ Input Current
Full Power-Down mode
2.00
±80 µA
0.1 µA
Power Requirements
Positive Supply Voltage
Positive Supply Current
Positive Supply Current
VDD
Operating Mode ext. VREF
IDD VDD=3.6V ^{Operating Mode int. VREF}
Fast Power-Down int. VREF
Full Power-Down
Operating Mode ext. VREF
IDD VDD=5.25V ^{Operating Mode int. VREF}
Fast Power-Down
Full Power-Down
2.7
5.25 V
0.85 1.0 mA
1.3 1.4 mA
250
300 _µA
0.5 4.0
1.00 1.3 mA
1.40 1.6 mA
250
300 _µA
0.5 4.0
Copyright © 2008, ZMD AG, Rev. 1.1
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
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