Z86C21 Datasheet, PDF (6/35 Pages) Zilog, Inc. – 8K ROM Z8 CMOS MICROCONTROLLER

PIN FUNCTIONS
Z86C21 MCU
WITH 8K ROM
/ROMless (input, active Low). This pin, when connected to
GND, disables the internal ROM and forces the device to
function as a Z86C91 ROMless Z8. For more details on the
ROMless version, refer to the Z86C91 product specifica-
tion. (Note: When left unconnected or pulled high to V ,
CC
the part functions as a normal Z86C21 ROM version). This
pin is only available on the 44-pin versions of the Z86C21.
/DS (output, active Low). Data Strobe is activated once for
each external memory transfer. For a READ operation,
data must be available prior to the trailing edge of /DS. For
WRITE operations, the falling edge of /DS indicates that
output data is valid.
/AS (output, active Low). Address Strobe is pulsed once at
the beginning of each machine cycle. Address output is
through Port 1 for all external programs. Memory address
transfers are valid at the trailing edge of /AS. Under
program control, /AS is placed in the high-impedance
state along with Ports 0 and 1, Data Strobe, and Read/
Write.
On the fifth clock after the /RESET is detected, an internal
RST signal is latched and held for an internal register count
of 18 external clocks, or for the duration of the external
/RESET, whichever is longer. During the reset cycle, /DS is
held active Low while /AS cycles at a rate of TpC2. When
/RESET is deactivated, program execution begins at loca-
tion 000C (HEX). Power-up reset time must be held Low for
50 ms, or until V is stable, whichever is longer.
CC
Port 0 (P07-P00). Port 0 is an 8-bit, nibble programmable,
bidirectional, TTL compatible port. These eight I/O lines
can be configured under software control as a nibble I/O
port, or as an address port for interfacing external memory.
When used as an I/O port, Port 0 may be placed under
handshake control. In this configuration, Port 3, lines P32
and P35 are used as the handshake control /DAV0 and
RDY0 (Data Available and Ready). Handshake signal
assignment is dictated by the I/O direction of the upper
nibble P07-P04. The lower nibble must have the same
direction as the upper nibble to be under handshake
control.
XTAL1, XTAL2 Crystal 1, Crystal 2 (time-based input and
output, respectively). These pins connect a parallel-reso-
nant crystal, ceramic resonator, LC, or any external single-
phase clock to the on-chip oscillator and buffer.
R//W (output, write Low). The Read/Write signal is Low
when the MCU is writing to the external program or data
memory.
For external memory references, Port 0 can provide ad-
dress bits A11-A8 (lower nibble) or A15-A8 (lower and
upper nibble) depending on the required address space.
If the address range requires 12 bits or less, the upper
nibble of Port 0 is programmed independently as I/O while
the lower nibble is used for addressing. If one or both
nibbles are needed for I/O operation, they must be config-
ured by writing to the Port 0 Mode register.
/RESET (input, active Low). To avoid asynchronous and
noisy reset problems, the Z86C21 is equipped with a reset
filter of four external clocks (4TpC). If the external /RESET
signal is less than 4TpC in duration, no reset occurs.
In ROMless mode, after a hardware reset, Port 0 lines are
defined as address lines A15-A8, and extended timing is
set to accommodate slow memory access. The initializa-
tion routine includes reconfiguration to eliminate this ex-
tended timing mode (Figure 5).
\6