Z86C21 Datasheet, PDF (1/35 Pages) Zilog, Inc. – 8K ROM Z8 CMOS MICROCONTROLLER

PRODUCT S PECIFICA TION
Z86C21 MCU
WITH 8K ROM
FEATURES
s 8-Bit CMOS MCU with 8 Kbytes of ROM
s 256 Byte Register File
- 236 Bytes of General-Purpose RAM
- 16 Bytes Control/Status Registers
- 4 Bytes for Ports
s 40-Pin DIP, 44-Pin PLCC or 44-Pin QFP Package
s 4.5V to 5.5V Operating Range
s Low Power Consumption: 220 mW (max) @ 16 MHz
s Fast instruction pointer: 1.0 µs @ 12 MHz
s Two Standby Modes: STOP and HALT
s 32 Input/Output Lines
Z86C21
8K ROM Z8^® CMOS
MICROCONTROLLER
s Full-Duplex UART
s All Digital Inputs are TTL Levels
s Auto Latches
s RAM and ROM Protect
s Two Programmable 8-Bit Counter/Timers each with
6-Bit Programmable Prescaler.
s Six Vectored, Priority Interrupts from Eight Different
Sources
s Clock Speeds: 12 and 16 MHz
s On-Chip Oscillator that Accepts a Crystal, Ceramic
Resonator, LC, or External Clock Drive.
GENERAL DESCRIPTION
The Z86C21 microcontroller is a member of the Z8 single-
chip microcontroller family with 8 Kbytes of ROM and
236 bytes of RAM. The device is packaged in a 40-pin DIP,
44-pin PLCC, or a 44-pin QFP with a ROMless pin option
available on the 44-pin versions only. With the ROM/
ROMless feature selectively, the Z86C21 offers both exter-
nal memory and preprogrammed ROM, making it well-
suited for high-volume applications or where code flexibil-
ity is required.
Zilog’s CMOS microcontroller offers fast execution, effi-
cient use of memory, sophisticated interrupts, input/output
bit manipulation capabilities, and easy hardware/software
system expansion along with low cost and low power
consumption.
The Z86C21 architecture is characterized by Zilog’s 8-bit
microcontroller core. The device offers a flexible I/O
scheme, an efficient register and address space structure,
multiplexed capabilities between address/data, I/O, and a
number of ancillary features that are useful in many indus-
trial and advanced scientific applications.
For applications demanding powerful I/O capabilities, the
Z86C21 provides 32 pins dedicated to input and output.
These lines are grouped into four ports. Each port consists
of eight lines, and is configurable under software control to
provide timing, status signals, serial or parallel
I/O with or without handshake, and an address/data bus
for interfacing external memory. There are three basic
address spaces available to support this configuration:
Program Memory, Data Memory, and 236 general-pur-
pose registers.
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